target/arm: Add FGWTE3_EL3 bit definitions
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260806172709.333300-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Aug 6, 2026 at 10:27 UTC
bf89d74e45882cc888970c4d061fe82ceff7587b
1 file changed
+24
target/arm/cpregs.h
+24
@@ -689,6 +689,30 @@ FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1)
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FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1)
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FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1)
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+FIELD(FGWTE3_EL3, ACTLR_EL3, 0, 1)
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+FIELD(FGWTE3_EL3, AFSR0_EL3, 1, 1)
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+FIELD(FGWTE3_EL3, AFSR1_EL3, 2, 1)
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+FIELD(FGWTE3_EL3, AMAIR_EL3, 3, 1)
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+FIELD(FGWTE3_EL3, AMAIR2_EL3, 4, 1)
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+FIELD(FGWTE3_EL3, GCSCR_EL3, 5, 1)
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+FIELD(FGWTE3_EL3, GCSPR_EL3, 6, 1)
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+FIELD(FGWTE3_EL3, GPCCR_EL3, 7, 1)
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+FIELD(FGWTE3_EL3, GPTBR_EL3, 8, 1)
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+FIELD(FGWTE3_EL3, MAIR_EL3, 9, 1)
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+FIELD(FGWTE3_EL3, MAIR2_EL3, 10, 1)
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+FIELD(FGWTE3_EL3, MDCR_EL3, 11, 1)
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+FIELD(FGWTE3_EL3, MECID_RL_A_EL3, 12, 1)
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+FIELD(FGWTE3_EL3, MPAM3_EL3, 13, 1)
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+FIELD(FGWTE3_EL3, PIR_EL3, 14, 1)
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+FIELD(FGWTE3_EL3, SCTLR_EL3, 15, 1)
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+FIELD(FGWTE3_EL3, SCTLR2_EL3, 16, 1)
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+FIELD(FGWTE3_EL3, SPMROOTCR_EL3, 17, 1)
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+FIELD(FGWTE3_EL3, TCR_EL3, 18, 1)
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+FIELD(FGWTE3_EL3, TPIDR_EL3, 19, 1)
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+FIELD(FGWTE3_EL3, TTBR0_EL3, 20, 1)
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+FIELD(FGWTE3_EL3, VBAR_EL3, 21, 1)
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+FIELD(FGWTE3_EL3, GPCBW_EL3, 22, 1)
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+
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FIELD(FGT, NXS, 13, 1) /* Honour HCR_EL2.FGTnXS to suppress FGT */
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/* Which fine-grained trap bit register to check, if any */
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FIELD(FGT, TYPE, 10, 3)