hw/riscv/riscv-iommu.c: check for reserved PTE bits
We need to fault if reserved PTE bits (60:54) are set. Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3554 Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com> Message-ID: <20260701121111.537654-2-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Daniel Henrique Barboza committed
Jul 1, 2026 at 09:11 UTC
c1d5ec3a2f4bbc9fdc120ba5697e8ad89e682e45
1 file changed
+2
hw/riscv/riscv-iommu.c
+2
@@ -469,6 +469,8 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
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if (!(pte & PTE_V)) {
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break; /* Invalid PTE */
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+ } else if (pte & PTE_RESERVED(false)) {
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+ break; /* Reserved PTE bits set */
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} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
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base = PPN_PHYS(ppn); /* Inner PTE, continue walking */
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} else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {