target/arm: Add feature predicates for SVE2.2 and SME2.2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260604234852.573178-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 4, 2026 at 16:48 UTC
c267a9c594e450e3341a761ca1215661ba1ebe1a
1 file changed
+16
-1
target/arm/cpu-features.h
+16
-1
@@ -1516,7 +1516,12 @@ static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
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static inline bool isar_feature_aa64_sve2p1(const ARMISARegisters *id)
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{
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- return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SVEVER) >=2;
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+ return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SVEVER) >= 2;
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+}
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+
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+static inline bool isar_feature_aa64_sve2p2(const ARMISARegisters *id)
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+{
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+ return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SVEVER) >= 3;
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}
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static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id)
@@ -1625,6 +1630,11 @@ static inline bool isar_feature_aa64_sme2p1(const ARMISARegisters *id)
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return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SMEVER) >= 2;
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}
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+static inline bool isar_feature_aa64_sme2p2(const ARMISARegisters *id)
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+{
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+ return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SMEVER) >= 3;
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+}
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+
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static inline bool isar_feature_aa64_f8cvt(const ARMISARegisters *id)
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{
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return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8CVT);
@@ -1688,6 +1698,11 @@ static inline bool isar_feature_aa64_sme2p1_or_sve2p1(const ARMISARegisters *id)
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return isar_feature_aa64_sme2p1(id) || isar_feature_aa64_sve2p1(id);
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}
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+static inline bool isar_feature_aa64_sme2p2_or_sve2p2(const ARMISARegisters *id)
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+{
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+ return isar_feature_aa64_sme2p2(id) || isar_feature_aa64_sve2p2(id);
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+}
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+
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static inline bool isar_feature_aa64_sme2_i16i64(const ARMISARegisters *id)
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{
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return isar_feature_aa64_sme2(id) && isar_feature_aa64_sme_i16i64(id);