target/arm: Implement FMMLA (FP8 to FP16) for SVE
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260609192110.752384-45-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 9, 2026 at 12:21 UTC
c2b46bc3a6ff341e6bcdc738e5f6250fe0d1e03b
3 files changed
+8
target/arm/cpu-features.h
+5
@@ -1728,6 +1728,11 @@ static inline bool isar_feature_aa64_sve2_f8mm8(const ARMISARegisters *id)
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return isar_feature_aa64_sve2(id) && isar_feature_aa64_f8mm8(id);
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}
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+static inline bool isar_feature_aa64_sve2_f8mm4(const ARMISARegisters *id)
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+{
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+ return isar_feature_aa64_sve2(id) && isar_feature_aa64_f8mm4(id);
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+}
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+
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static inline bool
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isar_feature_aa64_sme2_or_sve2_faminmax(const ARMISARegisters *id)
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{
target/arm/tcg/sve.decode
+1
@@ -1809,6 +1809,7 @@ FMMLA_s 01100100 10 1 ..... 111 001 ..... ..... @rda_rn_rm_ex esz=2
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FMMLA_d 01100100 11 1 ..... 111 001 ..... ..... @rda_rn_rm_ex esz=3
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FMMLA_sb 01100100 00 1 ..... 111 000 ..... ..... @rda_rn_rm_ex esz=2
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+FMMLA_hb 01100100 01 1 ..... 111 000 ..... ..... @rda_rn_rm_ex esz=1
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### SVE2 Memory Gather Load Group
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target/arm/tcg/translate-sve.c
+2
@@ -8477,3 +8477,5 @@ static bool do_fmmla_fp8(DisasContext *s, arg_rrrr_esz *a,
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TRANS_FEAT_NONSTREAMING(FMMLA_sb, aa64_sve2_f8mm8, do_fmmla_fp8, a,
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gen_helper_gvec_fmmla_sb)
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+TRANS_FEAT_NONSTREAMING(FMMLA_hb, aa64_sve2_f8mm4, do_fmmla_fp8, a,
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+ gen_helper_gvec_fmmla_hb)