target/mips: add Octeon CvmCount RDHWR support
Octeon exposes CvmCount through RDHWR register 31. Add the Octeon-only decode path, enable the corresponding HWREna bit for linux-user, and use an unsigned mask when checking HWREna so bit 31 is handled safely. For user-mode emulation, return host ticks as a monotonic counter source suitable for existing Octeon userspace code. In system mode, fall back to the existing CP0 Count value. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: James Hilliard <james.hilliard1@gmail.com> Message-ID: <20260608-mips-octeon-missing-insns-v2-v16-20-daef7a0d8b04@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
James Hilliard committed
Jun 8, 2026 at 12:59 UTC
c2fd17ec64451d3aa181623e056ca1ce019eddcd
5 files changed
+42
-1
target/mips/cpu.c
+1
@@ -320,6 +320,7 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type)
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env->CP0_HWREna |= 0x0000000F;
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if (env->insn_flags & INSN_OCTEON) {
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env->CP0_HWREna |= 0x40000000u;
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+ env->CP0_HWREna |= 0x80000000u;
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}
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if (env->CP0_Config1 & (1 << CP0C1_FP)) {
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env->CP0_Status |= (1 << CP0St_CU1);
target/mips/helper.h
+1
@@ -255,6 +255,7 @@ DEF_HELPER_1(rdhwr_ccres, tl, env)
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DEF_HELPER_1(rdhwr_performance, tl, env)
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DEF_HELPER_1(rdhwr_xnp, tl, env)
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DEF_HELPER_1(rdhwr_chord, tl, env)
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+DEF_HELPER_1(rdhwr_cvmcount, tl, env)
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DEF_HELPER_2(pmon, void, env, int)
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DEF_HELPER_1(wait, void, env)
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target/mips/tcg/op_helper.c
+12
-1
@@ -25,6 +25,7 @@
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#include "exec/memop.h"
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#include "fpu_helper.h"
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#include "qemu/crc32c.h"
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+#include "qemu/timer.h"
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#include <zlib.h>
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31
static inline target_ulong bitswap(target_ulong v)
@@ -209,7 +210,7 @@ target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
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static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc)
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{
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- if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) {
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+ if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1u << reg))) {
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return;
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}
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do_raise_exception(env, EXCP_RI, pc);
@@ -261,6 +262,16 @@ target_ulong helper_rdhwr_chord(CPUMIPSState *env)
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return env->octeon_crypto.chord;
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}
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+target_ulong helper_rdhwr_cvmcount(CPUMIPSState *env)
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+{
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+ check_hwrena(env, 31, GETPC());
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+#ifdef CONFIG_USER_ONLY
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+ return cpu_get_host_ticks();
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+#else
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+ return (uint32_t)cpu_mips_get_count(env);
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+#endif
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+}
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+
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void helper_pmon(CPUMIPSState *env, int function)
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{
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function /= 2;
target/mips/tcg/translate.c
+11
@@ -10933,6 +10933,17 @@ void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
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gen_helper_rdhwr_chord(t0, tcg_env);
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gen_store_gpr(t0, rt);
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break;
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+ case 31:
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+ if (!(ctx->insn_flags & INSN_OCTEON)) {
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+ gen_reserved_instruction(ctx);
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+ break;
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+ }
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+ translator_io_start(&ctx->base);
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+ gen_helper_rdhwr_cvmcount(t0, tcg_env);
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+ gen_store_gpr(t0, rt);
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+ gen_save_pc(ctx->base.pc_next + 4);
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+ ctx->base.is_jmp = DISAS_EXIT;
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+ break;
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default: /* Invalid */
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MIPS_INVAL("rdhwr");
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gen_reserved_instruction(ctx);
tests/tcg/mips/user/isa/octeon/octeon-insns.c
+17
@@ -330,6 +330,22 @@ static uint64_t octeon_cop2_gfm_mul_reflect_readback(uint64_t value)
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return rd;
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}
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+static uint64_t octeon_rdhwr31_non_decreasing(void)
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+{
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+ uint64_t first, second;
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+
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+ asm volatile(
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+ ".word 0x7c08f83b\n\t" /* rdhwr $8, $31 */
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+ ".word 0x7c09f83b\n\t" /* rdhwr $9, $31 */
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+ "move %[first], $8\n\t"
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+ "move %[second], $9\n\t"
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+ : [first] "=r" (first), [second] "=r" (second)
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+ :
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+ : "$8", "$9");
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+
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+ return second >= first;
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+}
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+
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int main(void)
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{
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assert(octeon_baddu(0x123, 0x0f0) == 0x13);
@@ -358,6 +374,7 @@ int main(void)
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0x0123456789abcdefULL) == 0xf7b3d591e6a2c480ULL);
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assert(octeon_cop2_gfm_mul_reflect_readback(
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0xfedcba9876543210ULL) == 0x084c2a6e195d3b7fULL);
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+ assert(octeon_rdhwr31_non_decreasing());
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return 0;
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}