target/riscv: Improve alignment in riscv_cpu_dump_state
Align all the CSR values. mcountinhibit is the longest CSR name at 13 characters, so use that width for PC, implicit state, and CSR names. Also remove the redundant '=' from the implicit state lines.t Signed-off-by: Anton Blanchard <antonb@tenstorrent.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260529053519.1224019-2-antonb@tenstorrent.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anton Blanchard committed
May 29, 2026 at 05:35 UTC
c34402df3a6e9c0d63298fc8ae3dee9683e45ce4
1 file changed
+5
-5
target/riscv/cpu.c
+5
-5
@@ -572,7 +572,7 @@ static void riscv_dump_csr(CPURISCVState *env, int csrno, FILE *f)
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* to do the filtering of the registers that are present.
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*/
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if (res == RISCV_EXCP_NONE) {
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- qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
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+ qemu_fprintf(f, " %-13s " TARGET_FMT_lx "\n",
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csr_ops[csrno].name, val);
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}
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}
@@ -601,17 +601,17 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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uint8_t *p;
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#if !defined(CONFIG_USER_ONLY)
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- qemu_fprintf(f, " %s %s\n", "priv = ", riscv_priv_str(env->priv));
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+ qemu_fprintf(f, " %-13s %s\n", "priv", riscv_priv_str(env->priv));
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if (riscv_has_ext(env, RVH)) {
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- qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled);
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+ qemu_fprintf(f, " %-13s %d\n", "V", env->virt_enabled);
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}
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if (cpu->cfg.ext_zicfilp) {
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- qemu_fprintf(f, " %s %d\n", "elp = ", env->elp);
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+ qemu_fprintf(f, " %-13s %d\n", "elp", env->elp);
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}
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#endif
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- qemu_fprintf(f, " %s %" PRIx64 "\n", "pc ", env->pc);
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+ qemu_fprintf(f, " %-13s %" PRIx64 "\n", "pc", env->pc);
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#ifndef CONFIG_USER_ONLY
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for (i = 0; i < ARRAY_SIZE(csr_ops); i++) {
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int csrno = i;