target/arm: Enable FEAT_SME_F8F16 for -cpu max
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260625015159.719300-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 24, 2026 at 18:51 UTC
c3da6e9f754b87f7f510e1096916f4fe76b7a4b1
3 files changed
+3
docs/system/arm/emulation.rst
+1
@@ -170,6 +170,7 @@ the following architecture extensions:
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- FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode)
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- FEAT_SME_F16F16 (Non-widening half-precision FP16 arithmetic for SME2)
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- FEAT_SME_F64F64 (Double-precision floating-point outer product instructions)
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+- FEAT_SME_F8F16 (SME2 ZA-targeting FP8 multiply-accumulate, dot product, and outer product to half-precision instructions)
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- FEAT_SME_F8F32 (SME2 ZA-targeting FP8 multiply-accumulate, dot product, and outer product to single-precision instructions)
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- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions)
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- FEAT_SME_LUTv2 (Lookup table instructions with 4-bit indices and 8-bit elements)
linux-user/aarch64/elfload.c
+1
@@ -236,6 +236,7 @@ abi_ulong get_elf_hwcap2(CPUState *cs)
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GET_FEATURE_ID(aa64_ssve_f8dp4, ARM_HWCAP2_A64_SME_SF8DP4);
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GET_FEATURE_ID(aa64_ssve_f8dp2, ARM_HWCAP2_A64_SME_SF8DP2);
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GET_FEATURE_ID(aa64_sme_f8f32, ARM_HWCAP2_A64_SME_F8F32);
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+ GET_FEATURE_ID(aa64_sme_f8f16, ARM_HWCAP2_A64_SME_F8F16);
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return hwcaps;
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}
target/arm/tcg/cpu64.c
+1
@@ -1393,6 +1393,7 @@ void aarch64_max_tcg_initfn(Object *obj)
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t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */
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t = FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */
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t = FIELD_DP64(t, ID_AA64SMFR0, F8F32, 1); /* FEAT_SME_F8F32 */
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+ t = FIELD_DP64(t, ID_AA64SMFR0, F8F16, 1); /* FEAT_SME_F8F16 */
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t = FIELD_DP64(t, ID_AA64SMFR0, F16F16, 1); /* FEAT_SME_F16F16 */
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t = FIELD_DP64(t, ID_AA64SMFR0, B16B16, 1); /* FEAT_SME_B16B16 */
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t = FIELD_DP64(t, ID_AA64SMFR0, I16I32, 5); /* FEAT_SME2 */