@samitouri / QOSamiQemu / commits / c4066c84cd

target/hexagon: initialize deferred sreg-write temps to current value

Unconditionally allocate and initialize the temp to the sreg's current value for every logged sreg write, rather than only allocating when need_commit is set or the register is SSR. Without this, reading a deferred sreg write within the same packet before it is committed can observe an uninitialized temp instead of the register's pre-packet value. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>

Brian Cain committed Jul 16, 2026 at 12:15 UTC c4066c84cdc200ba5752280829135bc389ed7eb6
1 file changed +3 -2
target/hexagon/translate.c
+3 -2
@@ -615,9 +615,10 @@ static void gen_start_packet(DisasContext *ctx)
615 }
616 for (i = 0; i < ctx->sreg_log_idx; i++) {
617 int reg_num = ctx->sreg_log[i];
618 - if (reg_num < HEX_SREG_GLB_START &&
619 - (ctx->need_commit || reg_num == HEX_SREG_SSR)) {
618 + if (reg_num < HEX_SREG_GLB_START) {
619 ctx->t_sreg_new_value[reg_num] = tcg_temp_new();
620 + tcg_gen_mov_tl(ctx->t_sreg_new_value[reg_num],
621 + hex_t_sreg[reg_num]);
622 }
623 }
624 for (i = 0; i < NUM_GREGS; i++) {