target/arm: Enable FEAT_F8F16MM for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260609192110.752384-46-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 9, 2026 at 12:21 UTC
c45b02cb24ee20ffee2508f50278b392526427eb
3 files changed
+3
docs/system/arm/emulation.rst
+1
@@ -67,6 +67,7 @@ the following architecture extensions:
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- FEAT_EPAC (Enhanced pointer authentication)
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- FEAT_ETS2 (Enhanced Translation Synchronization)
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- FEAT_EVT (Enhanced Virtualization Traps)
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+- FEAT_F8F16MM (8-bit floating-point matrix multiply-accumulate to half-precision)
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- FEAT_F8F32MM (8-bit floating-point matrix multiply-accumulate to single-precision)
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- FEAT_F32MM (Single-precision Matrix Multiplication)
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- FEAT_F64MM (Double-precision Matrix Multiplication)
linux-user/aarch64/elfload.c
+1
@@ -172,6 +172,7 @@ abi_ulong get_elf_hwcap(CPUState *cs)
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GET_FEATURE_ID(aa64_gcs, ARM_HWCAP_A64_GCS);
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GET_FEATURE_ID(aa64_cmpbr, ARM_HWCAP_A64_CMPBR);
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GET_FEATURE_ID(aa64_f8mm8, ARM_HWCAP_A64_F8MM8);
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+ GET_FEATURE_ID(aa64_f8mm4, ARM_HWCAP_A64_F8MM4);
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return hwcaps;
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}
target/arm/tcg/cpu64.c
+1
@@ -1404,6 +1404,7 @@ void aarch64_max_tcg_initfn(Object *obj)
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t = GET_IDREG(isar, ID_AA64FPFR0);
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t = FIELD_DP64(t, ID_AA64FPFR0, F8E5M2, 1); /* FEAT_FP8 */
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t = FIELD_DP64(t, ID_AA64FPFR0, F8E4M3, 1); /* FEAT_FP8 */
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+ t = FIELD_DP64(t, ID_AA64FPFR0, F8MM4, 1); /* FEAT_F8F16MM */
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t = FIELD_DP64(t, ID_AA64FPFR0, F8MM8, 1); /* FEAT_F8F32MM */
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t = FIELD_DP64(t, ID_AA64FPFR0, F8DP2, 1); /* FEAT_FP8DOT2 */
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t = FIELD_DP64(t, ID_AA64FPFR0, F8DP4, 1); /* FEAT_FP8DOT4 */