target/riscv: Reorder Smrnmi CPU fields above CPU reset line
Smrnmi CPU fields introduced by commit: #5db557f should be reset when the CPU resets, so move these fields above the CPU reset line. Fixes: 5db557f82bff ("target/riscv: Add Smrnmi CSRs") Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260528060007.717307-1-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang committed
May 28, 2026 at 14:00 UTC
c483b90ccd9b8cb3c7445c1b8f0dfbb5e03a6e5f
1 file changed
+9
-9
target/riscv/cpu.h
+9
-9
@@ -491,6 +491,15 @@ struct CPUArchState {
491
uint64_t hstateen[SMSTATEEN_MAX_COUNT];
492
uint64_t sstateen[SMSTATEEN_MAX_COUNT];
493
uint64_t henvcfg;
494
+
495
+ /* RNMI */
496
+ uint64_t mnscratch;
497
+ uint64_t mnepc;
498
+ uint64_t mncause; /* mncause without bit XLEN-1 set to 1 */
499
+ uint64_t mnstatus;
500
+ uint64_t rnmip;
501
+ uint64_t rnmi_irqvec;
502
+ uint64_t rnmi_excpvec;
503
#endif
504
505
/* Fields from here on are preserved across CPU reset. */
@@ -509,15 +518,6 @@ struct CPUArchState {
518
uint64_t kvm_timer_state;
519
uint64_t kvm_timer_frequency;
520
#endif /* CONFIG_KVM */
512
-
513
- /* RNMI */
514
- uint64_t mnscratch;
515
- uint64_t mnepc;
516
- uint64_t mncause; /* mncause without bit XLEN-1 set to 1 */
517
- uint64_t mnstatus;
518
- uint64_t rnmip;
519
- uint64_t rnmi_irqvec;
520
- uint64_t rnmi_excpvec;
521
};
522
523
/*