hw/riscv/boot: Replace cpu_to_le32() -> const_le32()
Rather than adapting the array endianness when it it filled, directly initialize the CODE words with the correct endianness. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Message-ID: <20260527201348.29511-9-philmd@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Philippe Mathieu-Daudé committed
May 27, 2026 at 22:13 UTC
c64fbc121996005f422ade58e3c53d0dc36f4f75
1 file changed
+13
-17
hw/riscv/boot.c
+13
-17
@@ -454,40 +454,36 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
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uint64_t kernel_entry,
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uint64_t fdt_load_addr)
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{
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- int i;
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const bool rv32 = riscv_is_32bit(harts);
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uint32_t reset_vec[CODE_WORDS + DATA_WORDS];
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- /* .text */
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- reset_vec[0] = 0x00000297; /* 1: auipc t0, %pcrel_hi(fw_dyn) */
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- reset_vec[1] = 0x02828613; /* addi a2, t0, %pcrel_lo(1b) */
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+ /* .text (RISC-V instructions are always little-endian) */
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+ reset_vec[0] = const_le32(0x00000297); /* 1: auipc t0, %pcrel_hi(fw_dyn) */
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+ reset_vec[1] = const_le32(0x02828613); /* addi a2, t0, %pcrel_lo(1b) */
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+ reset_vec[2] = const_le32(0xf1402573); /* csrr a0, mhartid */
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if (harts->harts[0].cfg.ext_zicsr) {
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- reset_vec[2] = 0xf1402573; /* csrr a0, mhartid */
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+ reset_vec[2] = const_le32(0xf1402573); /* csrr a0, mhartid */
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} else {
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/*
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* The Zicsr extension has been disabled, so let's ensure we don't
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* run the CSR instruction. Let's fill the address with a non
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* compressed nop.
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*/
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- reset_vec[2] = 0x00000013; /* addi x0, x0, 0 */
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+ reset_vec[2] = const_le32(0x00000013); /* addi x0, x0, 0 */
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}
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if (rv32) {
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- reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */
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- reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */
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+ reset_vec[3] = const_le32(0x0202a583); /* lw a1, 32(t0) */
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+ reset_vec[4] = const_le32(0x0182a283); /* lw t0, 24(t0) */
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} else {
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- reset_vec[3] = 0x0202b583; /* ld a1, 32(t0) */
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- reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */
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+ reset_vec[3] = const_le32(0x0202b583); /* ld a1, 32(t0) */
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+ reset_vec[4] = const_le32(0x0182b283); /* ld t0, 24(t0) */
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}
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- reset_vec[5] = 0x00028067; /* jr t0 */
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+ reset_vec[5] = const_le32(0x00028067); /* jr t0 */
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/* .data */
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- stq_p(&reset_vec[6], start_addr); /* start: .dword */
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- stq_p(&reset_vec[8], fdt_load_addr); /* fdt_laddr: .dword */
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+ stq_le_p(&reset_vec[6], start_addr); /* start: .dword */
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+ stq_le_p(&reset_vec[8], fdt_load_addr); /* fdt_laddr: .dword */
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- /* copy in the reset vector in little_endian byte order */
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- for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
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- reset_vec[i] = cpu_to_le32(reset_vec[i]);
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- }
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rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
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rom_base, &address_space_memory);
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riscv_rom_copy_firmware_info(machine, harts,