@samitouri / QOSamiQemu / commits / c7093e3704

tcg/x86_64: declare MO_ATOM_WITHIN16 host atomicity support

Just like aarch64's prepare_host_addr(), x86_64 should use MO_ATOM_WITHIN16 for the memop when it's capable. Unlike aarch64, which needs to check a CPU feature, x86 has been capable since P6 family processors and newer (see Intel SDM Vol. 3 §11.1.1). Since a 16-byte aligned region always fits within a 16-byte multiple sized cache line (x86_64 implementations always have cache lines of at least 64 bytes), then this enables riscv cpu models with Zama16b to use the fast path, just as cpu models without Zama16b do. Cc: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [rth: Update both atom_and_align_for_opc calls] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260707122819.114105-1-andrew.jones@oss.qualcomm.com>

Andrew Jones committed Jul 7, 2026 at 14:28 UTC c7093e3704ab5d0bef4fa44fb6fa76ff5565c89f

1 file changed +2 -2

tcg/x86_64/tcg-target.c.inc

+2 -2

@@ -1783,7 +1783,7 @@ bool tcg_target_has_memory_bswap(MemOp memop)

1783 * Reject 16-byte memop with 16-byte atomicity, i.e. VMOVDQA,

1784 * but do allow a pair of 64-bit operations, i.e. MOVBEQ.

1785 */

1786 - aa = atom_and_align_for_opc(tcg_ctx, memop, MO_ATOM_IFALIGN, true);

1786 + aa = atom_and_align_for_opc(tcg_ctx, memop, MO_ATOM_WITHIN16, true);

1787 return aa.atom < MO_128;

1788 }

1789

@@ -1934,7 +1934,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,

1934 *h = x86_guest_base;

1935 }

1936 h->base = addr;

1937 - h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128);

1937 + h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_WITHIN16, s_bits == MO_128);

1938 a_mask = (1 << h->aa.align) - 1;

1939

1940 if (tcg_use_softmmu) {