hw/misc/aspeed_hace: Support 64-bit DMA for the crypto command
The AST2700 crypto engine addresses DRAM with 64 bits, supplying the high half of the source, destination and context addresses through HACE80, HACE84 and HACE88. Add those registers and a crypt_get_addr() helper that combines the low and high halves when the SoC has 64-bit DMA, mirroring the hash engine. SoCs without 64-bit DMA (AST2500/AST2600/AST1030) ignore the high registers, so their behaviour is unchanged. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Kane Chen <kane_chen@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20260811060115.1849266-14-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Jamin Lin committed
Aug 11, 2026 at 06:01 UTC
c98058bb3d3464be0923ffd5f88937ecc57a0cac
1 file changed
+30
-3
hw/misc/aspeed_hace.c
+30
-3
@@ -57,6 +57,11 @@
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#define CRYPT_CTX_KEY_OFFSET 0x10
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#define CRYPT_CTX_SIZE 0x30
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+/* AST2700 64-bit DMA high address registers for the crypto command */
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+#define R_CRYPT_SRC_HI (0x80 / 4)
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+#define R_CRYPT_DEST_HI (0x84 / 4)
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+#define R_CRYPT_CONTEXT_HI (0x88 / 4)
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+
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#define R_STATUS (0x1c / 4)
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#define HASH_IRQ BIT(9)
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#define CRYPT_IRQ BIT(12)
@@ -670,6 +675,19 @@ static void crypt_be_add(uint8_t *ctr, size_t len, uint64_t add)
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}
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}
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+static uint64_t crypt_get_addr(AspeedHACEState *s, int reg, int reg_hi)
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+{
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+ AspeedHACEClass *ahc = ASPEED_HACE_GET_CLASS(s);
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+ uint64_t addr;
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+
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+ addr = deposit64(0, 0, 32, s->regs[reg]);
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+ if (ahc->has_dma64) {
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+ addr = deposit64(addr, 32, 32, s->regs[reg_hi]);
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+ }
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+
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+ return addr;
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+}
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+
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/*
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* Perform an AES/DES/3DES ECB/CBC operation. The source and destination are
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* either single contiguous buffers (direct access mode) or scatter-gather
@@ -717,7 +735,7 @@ static void do_crypt_operation(AspeedHACEState *s, uint32_t cmd)
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}
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/* Fetch the IV and key from the context buffer in DRAM. */
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- ctx_addr = s->regs[R_CRYPT_CONTEXT];
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+ ctx_addr = crypt_get_addr(s, R_CRYPT_CONTEXT, R_CRYPT_CONTEXT_HI);
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if (address_space_read(&s->dram_as, ctx_addr, MEMTXATTRS_UNSPECIFIED,
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ctx, sizeof(ctx))) {
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qemu_log_mask(LOG_GUEST_ERROR,
@@ -758,7 +776,7 @@ static void do_crypt_operation(AspeedHACEState *s, uint32_t cmd)
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dst_buf = g_malloc0(buf_len);
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/* Gather the source into the bounce buffer, per the selected mode. */
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- src_addr = s->regs[R_CRYPT_SRC];
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+ src_addr = crypt_get_addr(s, R_CRYPT_SRC, R_CRYPT_SRC_HI);
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if (sg_mode) {
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status = crypt_prepare_sg(s, src_addr, src_buf, len, false);
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} else {
@@ -794,7 +812,7 @@ static void do_crypt_operation(AspeedHACEState *s, uint32_t cmd)
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}
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/* Scatter the result back out, per the selected mode. */
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- dst_addr = s->regs[R_CRYPT_DEST];
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+ dst_addr = crypt_get_addr(s, R_CRYPT_DEST, R_CRYPT_DEST_HI);
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if (sg_mode) {
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status = crypt_prepare_sg(s, dst_addr, dst_buf, len, true);
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} else {
@@ -958,6 +976,15 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data,
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case R_HASH_KEY_BUFF_HI:
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data &= ahc->key_hi_mask;
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break;
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+ case R_CRYPT_SRC_HI:
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+ data &= ahc->src_hi_mask;
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+ break;
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+ case R_CRYPT_DEST_HI:
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+ data &= ahc->dest_hi_mask;
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+ break;
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+ case R_CRYPT_CONTEXT_HI:
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+ data &= ahc->key_hi_mask;
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+ break;
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default:
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break;
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}