target/arm: SME BFCVT, BFCVTN have "Alternate BFloat16 behaviors"
The Arm ARM A1.5.10 notes that some instructions have "Alternate Bfloat16 behaviors" when FPCR.AH == 1. We implement these using the FPST_AH and FPST_AH_F16 fp_status words. The list includes the SME BFVCT (single-precision to BFloat16) and BFCVTN, but we forgot to make those use FPST_AH_F16 when we implemented them. (We get the ASIMD and SVE insns on the list right.) Add the missing logic to select the right FPST. Cc: qemu-stable@nongnu.org Fixes: 465d36db0e1 ("target/arm: Implement SME2 BFCVT, BFCVTN, FCVT, FCVTN") Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260521180854.1744788-1-peter.maydell@linaro.org
Peter Maydell committed
May 21, 2026 at 19:08 UTC
ca33de98447c2c2825c1af73cfacf4f65a9bc6c6
1 file changed
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-2
target/arm/tcg/translate-sme.c
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@@ -1449,9 +1449,9 @@ static bool do_zz_fpst(DisasContext *s, arg_zz_n *a, int data,
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}
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TRANS_FEAT(BFCVT, aa64_sme2, do_zz_fpst, a, 0,
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- FPST_A64, gen_helper_sme2_bfcvt)
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+ s->fpcr_ah ? FPST_AH : FPST_A64, gen_helper_sme2_bfcvt)
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TRANS_FEAT(BFCVTN, aa64_sme2, do_zz_fpst, a, 0,
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- FPST_A64, gen_helper_sme2_bfcvtn)
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+ s->fpcr_ah ? FPST_AH : FPST_A64, gen_helper_sme2_bfcvtn)
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TRANS_FEAT(FCVT_n, aa64_sme2, do_zz_fpst, a, 0,
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FPST_A64, gen_helper_sme2_fcvt_n)
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TRANS_FEAT(FCVTN, aa64_sme2, do_zz_fpst, a, 0,