hw/i3c/dw-i3c: Add register RO field masks
Adds read-only register masks for the DwC I3C controller. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Patrick Venture <venture@google.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-10-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Jamin Lin committed
Feb 25, 2026 at 02:12 UTC
ca56779a7a39dc47591449724330d65aa44428a5
1 file changed
+40
hw/i3c/dw-i3c.c
+40
@@ -296,6 +296,45 @@ static const uint32_t dw_i3c_resets[DW_I3C_NR_REGS] = {
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[R_SLAVE_CONFIG] = 0x00000023,
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};
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+static const uint32_t dw_i3c_ro[DW_I3C_NR_REGS] = {
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+ [R_DEVICE_CTRL] = 0x04fffe00,
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+ [R_DEVICE_ADDR] = 0x7f807f80,
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+ [R_HW_CAPABILITY] = 0xffffffff,
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+ [R_IBI_QUEUE_STATUS] = 0xffffffff,
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+ [R_DATA_BUFFER_THLD_CTRL] = 0xf8f8f8f8,
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+ [R_IBI_QUEUE_CTRL] = 0xfffffff0,
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+ [R_RESET_CTRL] = 0xffffffc0,
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+ [R_SLV_EVENT_CTRL] = 0xffffff3f,
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+ [R_INTR_STATUS] = 0xffff809f,
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+ [R_INTR_STATUS_EN] = 0xffff8080,
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+ [R_INTR_SIGNAL_EN] = 0xffff8080,
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+ [R_INTR_FORCE] = 0xffff8000,
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+ [R_QUEUE_STATUS_LEVEL] = 0xffffffff,
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+ [R_DATA_BUFFER_STATUS_LEVEL] = 0xffffffff,
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+ [R_PRESENT_STATE] = 0xffffffff,
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+ [R_CCC_DEVICE_STATUS] = 0xffffffff,
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+ [R_I3C_VER_ID] = 0xffffffff,
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+ [R_I3C_VER_TYPE] = 0xffffffff,
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+ [R_DEVICE_ADDR_TABLE_POINTER] = 0xffffffff,
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+ [R_DEV_CHAR_TABLE_POINTER] = 0xffcbffff,
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+ [R_SLV_PID_VALUE] = 0xffff0fff,
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+ [R_SLV_CHAR_CTRL] = 0xffffffff,
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+ [A_VENDOR_SPECIFIC_REG_POINTER] = 0xffffffff,
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+ [R_SLV_MAX_LEN] = 0xffffffff,
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+ [R_MAX_READ_TURNAROUND] = 0xffffffff,
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+ [R_MAX_DATA_SPEED] = 0xffffffff,
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+ [R_SLV_INTR_REQ] = 0xfffffff0,
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+ [R_SLV_TSX_SYMBL_TIMING] = 0xffffffc0,
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+ [R_DEVICE_CTRL_EXTENDED] = 0xfffffff8,
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+ [R_SCL_I3C_OD_TIMING] = 0xff00ff00,
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+ [R_SCL_I3C_PP_TIMING] = 0xff00ff00,
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+ [R_SCL_I2C_FMP_TIMING] = 0xff000000,
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+ [R_SCL_EXT_TERMN_LCNT_TIMING] = 0x0000fff0,
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+ [R_BUS_IDLE_TIMING] = 0xfff00000,
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+ [R_EXTENDED_CAPABILITY] = 0xffffffff,
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+ [R_SLAVE_CONFIG] = 0xffffffff,
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+};
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+
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static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size)
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{
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DWI3C *s = DW_I3C(opaque);
@@ -324,6 +363,7 @@ static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value,
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trace_dw_i3c_write(s->id, offset, value);
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+ value &= ~dw_i3c_ro[addr];
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switch (addr) {
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case R_HW_CAPABILITY:
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case R_RESPONSE_QUEUE_PORT: