target/arm: Implement and enable FEAT_SSVE_BitPerm for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260826174213.614571-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Aug 26, 2026 at 10:42 UTC
cbdbd9177171e9018fa00130366af31aab91762b
5 files changed
+14
-6
docs/system/arm/emulation.rst
+1
@@ -192,6 +192,7 @@ the following architecture extensions:
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- FEAT_SME_MOP4 (Quarter-tile outer product instructions)
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- FEAT_SME_TMOP (Structured sparsity outer product instructions)
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- FEAT_SSVE_AES (Streaming SVE Mode Advanced Encryption Standard and 128-bit polynomial multiply long instructions)
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+- FEAT_SSVE_BitPerm (Streaming Scalable Vector Bit Permutes instructions)
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- FEAT_SSVE_FEXPA (Streaming FEXPA instruction)
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- FEAT_SSVE_FP8DOT2 (SVE2 FP8 2-way dot product to half-precision instructions in Streaming SVE mode)
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- FEAT_SSVE_FP8DOT4 (SVE2 FP8 4-way dot product to single-precision instructions in Streaming SVE mode)
linux-user/aarch64/elfload.c
+1
@@ -181,6 +181,7 @@ abi_ulong get_elf_hwcap(CPUState *cs)
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GET_FEATURE_ID(aa64_sve2p2, ARM_HWCAP_A64_SVE2P2);
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GET_FEATURE_ID(aa64_sme2p2, ARM_HWCAP_A64_SME2P2);
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GET_FEATURE_ID(aa64_sve_bfscale, ARM_HWCAP_A64_SVE_BFSCALE);
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+ GET_FEATURE_ID(aa64_ssve_bitperm, ARM_HWCAP_A64_SME_SBITPERM);
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return hwcaps;
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}
target/arm/cpu-features.h
+5
@@ -1610,6 +1610,11 @@ static inline bool isar_feature_aa64_ssve_aes(const ARMISARegisters *id)
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return FIELD_EX64_IDREG(id, ID_AA64SMFR0, AES);
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}
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+static inline bool isar_feature_aa64_ssve_bitperm(const ARMISARegisters *id)
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+{
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+ return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SBITPERM);
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+}
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+
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static inline bool isar_feature_aa64_ssve_f8fma(const ARMISARegisters *id)
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{
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return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SF8FMA);
target/arm/tcg/cpu64.c
+1
@@ -1484,6 +1484,7 @@ void aarch64_max_v9_tcg_initfn(Object *obj)
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t = FIELD_DP64(t, ID_AA64SMFR0, STMOP, 1); /* v9.4: FEAT_SME_TMOP */
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t = FIELD_DP64(t, ID_AA64SMFR0, SFEXPA, 1); /* v9.4: FEAT_SSVE_FEXPA */
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t = FIELD_DP64(t, ID_AA64SMFR0, AES, 1); /* v9.5: FEAT_SSVE_AES */
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+ t = FIELD_DP64(t, ID_AA64SMFR0, SBITPERM, 1); /* v9.4: FEAT_SSVE_BitPerm */
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t = FIELD_DP64(t, ID_AA64SMFR0, SF8DP2, 1); /* v9.2: FEAT_SSVE_FP8DOT2 */
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t = FIELD_DP64(t, ID_AA64SMFR0, SF8DP4, 1); /* v9.2: FEAT_SSVE_FP8DOT4 */
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t = FIELD_DP64(t, ID_AA64SMFR0, SF8FMA, 1); /* v9.2: FEAT_SSVE_FP8FMA */
target/arm/tcg/translate-sve.c
+6
-6
@@ -7430,22 +7430,22 @@ static gen_helper_gvec_3 * const bext_fns[4] = {
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gen_helper_sve2_bext_b, gen_helper_sve2_bext_h,
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gen_helper_sve2_bext_s, gen_helper_sve2_bext_d,
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};
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-TRANS_FEAT_NONSTREAMING(BEXT, aa64_sve_bitperm, gen_gvec_ool_arg_zzz,
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- bext_fns[a->esz], a, 0)
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+TRANS_FEAT_STREAMING_IF(BEXT, aa64_sve_bitperm, aa64_ssve_bitperm,
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+ gen_gvec_ool_arg_zzz, bext_fns[a->esz], a, 0)
7435
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static gen_helper_gvec_3 * const bdep_fns[4] = {
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gen_helper_sve2_bdep_b, gen_helper_sve2_bdep_h,
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gen_helper_sve2_bdep_s, gen_helper_sve2_bdep_d,
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};
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-TRANS_FEAT_NONSTREAMING(BDEP, aa64_sve_bitperm, gen_gvec_ool_arg_zzz,
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- bdep_fns[a->esz], a, 0)
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+TRANS_FEAT_STREAMING_IF(BDEP, aa64_sve_bitperm, aa64_ssve_bitperm,
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+ gen_gvec_ool_arg_zzz, bdep_fns[a->esz], a, 0)
7442
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static gen_helper_gvec_3 * const bgrp_fns[4] = {
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gen_helper_sve2_bgrp_b, gen_helper_sve2_bgrp_h,
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gen_helper_sve2_bgrp_s, gen_helper_sve2_bgrp_d,
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};
7447
-TRANS_FEAT_NONSTREAMING(BGRP, aa64_sve_bitperm, gen_gvec_ool_arg_zzz,
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- bgrp_fns[a->esz], a, 0)
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+TRANS_FEAT_STREAMING_IF(BGRP, aa64_sve_bitperm, aa64_ssve_bitperm,
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+ gen_gvec_ool_arg_zzz, bgrp_fns[a->esz], a, 0)
7449
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static gen_helper_gvec_3 * const cadd_fns[4] = {
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gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h,