target/loongarch: Use sys_state in op_helper.c when accessing CSR registers
When accessing CSR registers in file op_helper.c, use sys_state rather than env. There is no function change. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@mailo.com> Tested-by: Song Gao <gaosong@loongson.cn> Message-ID: <20260605083756.175598-1-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
Bibo Mao committed
Jun 5, 2026 at 16:37 UTC
cd25648460f6b6032d153ef0068e9bd21cbd1cd2
1 file changed
+26
-19
target/loongarch/tcg/op_helper.c
+26
-19
@@ -46,16 +46,20 @@ target_ulong helper_bitswap(target_ulong v)
46
/* loongarch assert op */
47
void helper_asrtle_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
48
{
49
+ CPUSysState *sys = env_sys(env);
50
+
51
if (rj > rk) {
50
- env->CSR_BADV = rj;
52
+ sys->CSR_BADV = rj;
53
do_raise_exception(env, EXCCODE_BCE, GETPC());
54
}
55
}
56
57
void helper_asrtgt_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
58
{
59
+ CPUSysState *sys = env_sys(env);
60
+
61
if (rj <= rk) {
58
- env->CSR_BADV = rj;
62
+ sys->CSR_BADV = rj;
63
do_raise_exception(env, EXCCODE_BCE, GETPC());
64
}
65
}
@@ -91,9 +95,10 @@ uint64_t helper_rdtime_d(CPULoongArchState *env)
95
#else
96
uint64_t plv;
97
LoongArchCPU *cpu = env_archcpu(env);
98
+ CPUSysState *sys = env_sys(env);
99
95
- plv = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
96
- if (extract64(env->CSR_MISC, R_CSR_MISC_DRDTL_SHIFT + plv, 1)) {
100
+ plv = FIELD_EX64(sys->CSR_CRMD, CSR_CRMD, PLV);
101
+ if (extract64(sys->CSR_MISC, R_CSR_MISC_DRDTL_SHIFT + plv, 1)) {
102
do_raise_exception(env, EXCCODE_IPE, GETPC());
103
}
104
@@ -105,26 +110,28 @@ uint64_t helper_rdtime_d(CPULoongArchState *env)
110
void helper_ertn(CPULoongArchState *env)
111
{
112
uint64_t csr_pplv, csr_pie;
108
- if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
109
- csr_pplv = FIELD_EX64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV);
110
- csr_pie = FIELD_EX64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE);
111
-
112
- env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0);
113
- env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 0);
114
- env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 1);
115
- set_pc(env, env->CSR_TLBRERA);
113
+ CPUSysState *sys = env_sys(env);
114
+
115
+ if (FIELD_EX64(sys->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
116
+ csr_pplv = FIELD_EX64(sys->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV);
117
+ csr_pie = FIELD_EX64(sys->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE);
118
+
119
+ sys->CSR_TLBRERA = FIELD_DP64(sys->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0);
120
+ sys->CSR_CRMD = FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, DA, 0);
121
+ sys->CSR_CRMD = FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, PG, 1);
122
+ set_pc(env, sys->CSR_TLBRERA);
123
qemu_log_mask(CPU_LOG_INT, "%s: TLBRERA " TARGET_FMT_lx "\n",
117
- __func__, env->CSR_TLBRERA);
124
+ __func__, sys->CSR_TLBRERA);
125
} else {
119
- csr_pplv = FIELD_EX64(env->CSR_PRMD, CSR_PRMD, PPLV);
120
- csr_pie = FIELD_EX64(env->CSR_PRMD, CSR_PRMD, PIE);
126
+ csr_pplv = FIELD_EX64(sys->CSR_PRMD, CSR_PRMD, PPLV);
127
+ csr_pie = FIELD_EX64(sys->CSR_PRMD, CSR_PRMD, PIE);
128
122
- set_pc(env, env->CSR_ERA);
129
+ set_pc(env, sys->CSR_ERA);
130
qemu_log_mask(CPU_LOG_INT, "%s: ERA " TARGET_FMT_lx "\n",
124
- __func__, env->CSR_ERA);
131
+ __func__, sys->CSR_ERA);
132
}
126
- env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, csr_pplv);
127
- env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, csr_pie);
133
+ sys->CSR_CRMD = FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, PLV, csr_pplv);
134
+ sys->CSR_CRMD = FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, IE, csr_pie);
135
136
env->lladdr = 1;
137
}