target/riscv: Make pmp.h target_ulong agnostic
The pmp.h header is exposed through cpu.h. pmp_table_t is also used in CPUArchState. CSR declarations are only used in target/ and are moved to csr.h. In pmp.h, addr_reg is widened to 64 bits and the privilege mode parameter is fixed to 8 bits, similar to previous commits. Note, the cpu/pmp/entry and cpu/pmp VMSTATE versions are bumped, breaking migration from older versions. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260520125406.28693-26-anjo@rev.ng> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anton Johansson committed
May 20, 2026 at 14:54 UTC
ce2bee50a7eff3cf858ba4388b97c58eebbe7d29
4 files changed
+28
-23
target/riscv/csr.h
+12
@@ -87,4 +87,16 @@ extern const RISCVCSR th_csr_list[];
87
/* Implemented in mips_csr.c */
88
extern const RISCVCSR mips_csr_list[];
89
90
+/* PMP CSRs, defined in pmp.c */
91
+void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
92
+ target_ulong val);
93
+target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
94
+
95
+void mseccfg_csr_write(CPURISCVState *env, uint64_t val);
96
+uint64_t mseccfg_csr_read(CPURISCVState *env);
97
+
98
+void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
99
+ target_ulong val);
100
+target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
101
+
102
#endif /* RISCV_CSR_H */
target/riscv/machine.c
+5
-5
@@ -49,10 +49,10 @@ static int pmp_post_load(void *opaque, int version_id)
49
50
static const VMStateDescription vmstate_pmp_entry = {
51
.name = "cpu/pmp/entry",
52
- .version_id = 1,
53
- .minimum_version_id = 1,
52
+ .version_id = 2,
53
+ .minimum_version_id = 2,
54
.fields = (const VMStateField[]) {
55
- VMSTATE_UINTTL(addr_reg, pmp_entry_t),
55
+ VMSTATE_UINT64(addr_reg, pmp_entry_t),
56
VMSTATE_UINT8(cfg_reg, pmp_entry_t),
57
VMSTATE_END_OF_LIST()
58
}
@@ -60,8 +60,8 @@ static const VMStateDescription vmstate_pmp_entry = {
60
61
static const VMStateDescription vmstate_pmp = {
62
.name = "cpu/pmp",
63
- .version_id = 1,
64
- .minimum_version_id = 1,
63
+ .version_id = 2,
64
+ .minimum_version_id = 2,
65
.needed = pmp_needed,
66
.post_load = pmp_post_load,
67
.fields = (const VMStateField[]) {
target/riscv/pmp.c
+6
-4
@@ -23,6 +23,7 @@
23
#include "qemu/log.h"
24
#include "qapi/error.h"
25
#include "cpu.h"
26
+#include "target/riscv/csr.h"
27
#include "trace.h"
28
#include "exec/cputlb.h"
29
#include "exec/page-protection.h"
@@ -317,7 +318,7 @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, hwaddr addr)
318
*/
319
static bool pmp_hart_has_privs_default(CPURISCVState *env, pmp_priv_t privs,
320
pmp_priv_t *allowed_privs,
320
- target_ulong mode)
321
+ privilege_mode_t mode)
322
{
323
bool ret;
324
@@ -380,8 +381,9 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, pmp_priv_t privs,
381
* have no functional impact in QEMU emulation.
382
*/
383
bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr,
383
- target_ulong size, pmp_priv_t privs,
384
- pmp_priv_t *allowed_privs, target_ulong mode)
384
+ int size, pmp_priv_t privs,
385
+ pmp_priv_t *allowed_privs,
386
+ privilege_mode_t mode)
387
{
388
int i = 0;
389
int pmp_size = 0;
@@ -732,7 +734,7 @@ uint64_t mseccfg_csr_read(CPURISCVState *env)
734
* To avoid this we return a size of 1 (which means no caching) if the PMP
735
* region only covers partial of the TLB page.
736
*/
735
-target_ulong pmp_get_tlb_size(CPURISCVState *env, hwaddr addr)
737
+uint64_t pmp_get_tlb_size(CPURISCVState *env, hwaddr addr)
738
{
739
hwaddr pmp_sa;
740
hwaddr pmp_ea;
target/riscv/pmp.h
+5
-14
@@ -22,7 +22,6 @@
22
#ifndef RISCV_PMP_H
23
#define RISCV_PMP_H
24
25
-#include "exec/target_long.h"
25
#include "cpu.h"
26
27
typedef enum {
@@ -52,7 +51,7 @@ typedef enum {
51
} mseccfg_field_t;
52
53
typedef struct {
55
- target_ulong addr_reg;
54
+ uint64_t addr_reg;
55
uint8_t cfg_reg;
56
} pmp_entry_t;
57
@@ -67,21 +66,13 @@ typedef struct {
66
uint32_t num_rules;
67
} pmp_table_t;
68
70
-void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
71
- target_ulong val);
72
-target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
69
+typedef struct CPUArchState CPURISCVState;
70
74
-void mseccfg_csr_write(CPURISCVState *env, uint64_t val);
75
-uint64_t mseccfg_csr_read(CPURISCVState *env);
76
-
77
-void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
78
- target_ulong val);
79
-target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
71
bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr,
81
- target_ulong size, pmp_priv_t privs,
72
+ int size, pmp_priv_t privs,
73
pmp_priv_t *allowed_privs,
83
- target_ulong mode);
84
-target_ulong pmp_get_tlb_size(CPURISCVState *env, hwaddr addr);
74
+ privilege_mode_t mode);
75
+uint64_t pmp_get_tlb_size(CPURISCVState *env, hwaddr addr);
76
void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
77
void pmp_update_rule_nums(CPURISCVState *env);
78
uint32_t pmp_get_num_rules(CPURISCVState *env);