tests/tcg/riscv64: add misa write test
Link: https://lore.kernel.org/r/20260321144554.606417-2-npiggin@gmail.com Suggested-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Vladimir Isaev <vvisaev@gmail.com> Message-ID: <20260817150653.40357-3-vvisaev@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Vladimir Isaev committed
Aug 17, 2026 at 18:06 UTC
ce781055ff61308df9c4f9546c72e09b6908fe06
2 files changed
+92
tests/tcg/riscv64/Makefile.softmmu-target
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@@ -67,5 +67,9 @@ EXTRA_RUNS += run-test-zicclsm-off
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run-test-zicclsm-off: test-zicclsm-off
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$(call run-test, $<, $(QEMU) -cpu rv64$(comma)v=true$(comma)zfh=true$(comma)zicclsm=false $(QEMU_OPTS)$<)
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+EXTRA_RUNS += run-test-misa-w
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+run-test-misa-w: test-misa-w
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+ $(call run-test, $<, $(QEMU) -cpu rv64$(comma)x-misa-w=true$(comma)c=true$(comma)v=true $(QEMU_OPTS)$<)
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+
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# We don't currently support the multiarch system tests
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undefine MULTIARCH_TESTS
tests/tcg/riscv64/test-misa-w.S
new
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@@ -0,0 +1,88 @@
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+/*
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+ * Test for MISA changing C and related IALIGN alignment cases
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+ *
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+ * This test verifies that the "C" extension can be cleared and set in MISA,
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+ * that a branch to 2-byte aligned instructions can be executed when "C" is
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+ * enabled, and that a write to MISA which would increase IALIGN and cause
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+ * the next instruction to be unaligned is ignored.
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+ *
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#define RVC (1 << ('C'-'A'))
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+#define RVV (1 << ('V'-'A'))
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+
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+.option norvc
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+ .text
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+ .global _start
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+_start:
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+ lla t0, trap
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+ csrw mtvec, t0
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+
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+ csrr t0, misa
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+ li t1, RVC
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+ not t1, t1
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+ and t0, t0, t1
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+ csrw misa, t0
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+ csrr t1, misa
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+ li a0, 2 # fail code
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+ bne t0, t1, _exit # Could not clear RVC in MISA
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+
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+ li t1, RVC
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+ or t0, t0, t1
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+ csrw misa, t0
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+ csrr t1, misa
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+ li a0, 3 # fail code
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+ bne t0, t1, _exit # Could not set RVC in MISA
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+
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+ j unalign
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+. = . + 2
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+unalign:
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+
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+ li t1, RVC
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+ not t1, t1
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+ and t0, t0, t1
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+ csrw misa, t0
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+ csrr t1, misa
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+ li a0, 4 # fail code
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+ beq t0, t1, _exit # Was able to clear RVC in MISA
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+
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+ li t0, (RVC|RVV)
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+ not t0, t0
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+ and t0, t0, t1
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+ csrw misa, t0
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+ csrr t0, misa
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+ li a0, 5 # fail code
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+ bne t0, t1, _exit # MISA write was not ignored (RVV was cleared)
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+
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+ j realign
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+. = . + 2
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+realign:
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+
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+ # Success!
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+ li a0, 0
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+ j _exit
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+
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+trap:
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+ # Any trap is a fail code 1
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+ li a0, 1
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+
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+# Exit code in a0
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+_exit:
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+ lla a1, semiargs
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+ li t0, 0x20026 # ADP_Stopped_ApplicationExit
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+ sd t0, 0(a1)
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+ sd a0, 8(a1)
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+ li a0, 0x20 # TARGET_SYS_EXIT_EXTENDED
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+
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+ # Semihosting call sequence
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+ .balign 16
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+ slli zero, zero, 0x1f
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+ ebreak
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+ srai zero, zero, 0x7
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+ j .
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+
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+ .data
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+ .balign 16
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+semiargs:
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+ .space 16