amd_iommu: Generate XT interrupts when xt support is enabled
When MMIO 0x18[IntCapXTEn]=1, interrupts originating from the IOMMU itself are sent based on the programming in XT IOMMU Interrupt Control Registers in MMIO 0x170-0x180 instead of the programming in the IOMMU's MSI capability registers. The guest programs these registers with appropriate vector and destination ID instead of writing to PCI MSI capability. Current AMD vIOMMU is capable of generating interrupts only through PCI MSI capability and does not care about xt mode. Because of this AMD vIOMMU cannot generate event log interrupts when the guest has enabled xt mode. Introduce a new flag "intcapxten" which is set when guest writes control register [IntCapXTEn] (bit 51) and use vector and destination field in the XT MMIO register (0x170) to support XT mode. Signed-off-by: Sairaj Kodilkar <sarunkod@amd.com> Reviewed-by: Vasant Hegde <vasant.hegde@amd.com> Reviewed-by: Alejandro Jimenez <alejandro.j.jimenez@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20260302115130.5903-4-sarunkod@amd.com>
Sairaj Kodilkar committed
Mar 2, 2026 at 17:21 UTC
cf0210df65aa4f582e444b910c950e2b4a80b194
3 files changed
+59
-6
hw/i386/amd_iommu.c
+41
-6
@@ -192,18 +192,38 @@ static void amdvi_assign_andq(AMDVIState *s, hwaddr addr, uint64_t val)
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amdvi_writeq_raw(s, addr, amdvi_readq(s, addr) & val);
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}
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+static void amdvi_build_xt_msi_msg(AMDVIState *s, MSIMessage *msg)
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+{
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+ union mmio_xt_intr xt_reg;
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+ struct X86IOMMUIrq irq;
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+
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+ xt_reg.val = amdvi_readq(s, AMDVI_MMIO_XT_GEN_INTR);
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+
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+ irq.vector = xt_reg.vector;
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+ irq.delivery_mode = xt_reg.delivery_mode;
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+ irq.dest_mode = xt_reg.destination_mode;
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+ irq.dest = (xt_reg.destination_hi << 24) | xt_reg.destination_lo;
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+ irq.trigger_mode = 0;
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+ irq.redir_hint = 0;
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+
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+ x86_iommu_irq_to_msi_message(&irq, msg);
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+}
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+
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static void amdvi_generate_msi_interrupt(AMDVIState *s)
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{
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MSIMessage msg = {};
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- MemTxAttrs attrs = {
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- .requester_id = pci_requester_id(&s->pci->dev)
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- };
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202
- if (msi_enabled(&s->pci->dev)) {
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+ if (s->intcapxten) {
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+ trace_amdvi_generate_msi_interrupt("XT GEN");
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+ amdvi_build_xt_msi_msg(s, &msg);
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+ } else if (msi_enabled(&s->pci->dev)) {
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+ trace_amdvi_generate_msi_interrupt("MSI");
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msg = msi_get_message(&s->pci->dev, 0);
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- address_space_stl_le(&address_space_memory, msg.address, msg.data,
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- attrs, NULL);
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+ } else {
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+ trace_amdvi_generate_msi_interrupt("NO MSI");
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+ return;
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}
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+ apic_get_class(NULL)->send_msi(&msg);
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}
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static uint32_t get_next_eventlog_entry(AMDVIState *s)
@@ -1538,6 +1558,7 @@ const char *amdvi_mmio_get_name(hwaddr addr)
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MMIO_REG_TO_STRING(AMDVI_MMIO_PPR_BASE);
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MMIO_REG_TO_STRING(AMDVI_MMIO_PPR_HEAD);
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MMIO_REG_TO_STRING(AMDVI_MMIO_PPR_TAIL);
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+ MMIO_REG_TO_STRING(AMDVI_MMIO_XT_GEN_INTR);
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#undef MMIO_REG_TO_STRING
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default:
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return "UNHANDLED";
@@ -1581,6 +1602,15 @@ static void amdvi_handle_control_write(AMDVIState *s)
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s->ga_enabled = !!(control & AMDVI_MMIO_CONTROL_GAEN);
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s->xten = !!(control & AMDVI_MMIO_CONTROL_XTEN) && s->xtsup &&
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s->ga_enabled;
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+ /*
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+ * IntCapXTEn controls whether IOMMU-originated interrupts are sent based
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+ * on the information in XT IOMMU Interrupt Control Registers rather than
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+ * the IOMMU’s MSI capability registers. Therefore it requires IOMMU
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+ * x2APIC support capabilities (i.e. XTSup=1), but it is independent of
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+ * whether a driver chooses to enable x2APIC mode for interrupt remapping
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+ * (i.e. XTEn=1).
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+ */
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+ s->intcapxten = !!(control & AMDVI_MMIO_CONTROL_INTCAPXTEN) && s->xtsup;
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/* update the flags depending on the control register */
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if (s->cmdbuf_enabled) {
@@ -1790,6 +1820,9 @@ static void amdvi_mmio_write(void *opaque, hwaddr addr, uint64_t val,
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case AMDVI_MMIO_STATUS:
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amdvi_mmio_reg_write(s, size, val, addr);
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break;
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+ case AMDVI_MMIO_XT_GEN_INTR:
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+ amdvi_mmio_reg_write(s, size, val, addr);
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+ break;
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}
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}
1828
@@ -2440,6 +2473,7 @@ static void amdvi_init(AMDVIState *s)
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s->enabled = false;
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s->cmdbuf_enabled = false;
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s->xten = false;
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+ s->intcapxten = false;
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/* reset MMIO */
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memset(s->mmior, 0, AMDVI_MMIO_SIZE);
@@ -2510,6 +2544,7 @@ static const VMStateDescription vmstate_xt = {
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_BOOL(xten, AMDVIState),
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+ VMSTATE_BOOL(intcapxten, AMDVIState),
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VMSTATE_END_OF_LIST()
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}
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};
hw/i386/amd_iommu.h
+17
@@ -53,6 +53,7 @@
53
#define AMDVI_MMIO_EXCL_BASE 0x0020
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#define AMDVI_MMIO_EXCL_LIMIT 0x0028
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#define AMDVI_MMIO_EXT_FEATURES 0x0030
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+#define AMDVI_MMIO_XT_GEN_INTR 0x0170
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#define AMDVI_MMIO_COMMAND_HEAD 0x2000
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#define AMDVI_MMIO_COMMAND_TAIL 0x2008
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#define AMDVI_MMIO_EVENT_HEAD 0x2010
@@ -103,6 +104,7 @@
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#define AMDVI_MMIO_CONTROL_CMDBUFLEN (1ULL << 12)
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#define AMDVI_MMIO_CONTROL_GAEN (1ULL << 17)
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#define AMDVI_MMIO_CONTROL_XTEN (1ULL << 50)
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+#define AMDVI_MMIO_CONTROL_INTCAPXTEN (1ULL << 51)
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/* MMIO status register bits */
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#define AMDVI_MMIO_STATUS_CMDBUF_RUN (1 << 4)
@@ -338,6 +340,20 @@ struct irte_ga {
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union irte_ga_hi hi;
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};
342
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+union mmio_xt_intr {
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+ uint64_t val;
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+ struct {
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+ uint64_t rsvd_1:2,
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+ destination_mode:1,
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+ rsvd_2:5,
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+ destination_lo:24,
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+ vector:8,
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+ delivery_mode:1,
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+ rsvd_3:15,
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+ destination_hi:8;
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+ };
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+};
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+
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#define TYPE_AMD_IOMMU_DEVICE "amd-iommu"
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OBJECT_DECLARE_SIMPLE_TYPE(AMDVIState, AMD_IOMMU_DEVICE)
359
@@ -416,6 +432,7 @@ struct AMDVIState {
432
bool ga_enabled;
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bool xtsup; /* xtsup=on command line */
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bool xten; /* guest controlled, x2apic mode enabled */
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+ bool intcapxten; /* guest controlled, IOMMU x2apic interrupts enabled */
436
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/* DMA address translation */
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bool dma_remap;
hw/i386/trace-events
+1
@@ -118,6 +118,7 @@ amdvi_ir_intctl(uint8_t val) "int_ctl 0x%"PRIx8
118
amdvi_ir_target_abort(const char *str) "%s"
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amdvi_ir_delivery_mode(const char *str) "%s"
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amdvi_ir_irte_ga_val(uint64_t hi, uint64_t lo) "hi 0x%"PRIx64" lo 0x%"PRIx64
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+amdvi_generate_msi_interrupt(const char *str) "Mode: %s"
122
123
# vmport.c
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vmport_register(unsigned char command, void *func, void *opaque) "command: 0x%02x func: %p opaque: %p"