hw/riscv: Mark RISC-V specific peripherals as little-endian
These devices are only used by the RISC-V targets, which are only built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_LITTLE_ENDIAN (besides, the DEVICE_BIG_ENDIAN case isn't tested). Simplify directly using DEVICE_LITTLE_ENDIAN. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20260318103122.97244-2-philmd@linaro.org>
Philippe Mathieu-Daudé committed
Dec 10, 2025 at 12:50 UTC
cf430fa1f1b98d274c98bd87a100cf6153c3d80b
11 files changed
+11
-11
hw/char/ibex_uart.c
+1
-1
@@ -470,7 +470,7 @@ static void fifo_trigger_update(void *opaque)
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static const MemoryRegionOps ibex_uart_ops = {
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.read = ibex_uart_read,
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.write = ibex_uart_write,
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- .endianness = DEVICE_NATIVE_ENDIAN,
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+ .endianness = DEVICE_LITTLE_ENDIAN,
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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};
hw/char/shakti_uart.c
+1
-1
@@ -103,7 +103,7 @@ static void shakti_uart_write(void *opaque, hwaddr addr,
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static const MemoryRegionOps shakti_uart_ops = {
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.read = shakti_uart_read,
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.write = shakti_uart_write,
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- .endianness = DEVICE_NATIVE_ENDIAN,
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+ .endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {.min_access_size = 1, .max_access_size = 4},
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.valid = {.min_access_size = 1, .max_access_size = 4},
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};
hw/char/sifive_uart.c
+1
-1
@@ -236,7 +236,7 @@ static void fifo_trigger_update(void *opaque)
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static const MemoryRegionOps sifive_uart_ops = {
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.read = sifive_uart_read,
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.write = sifive_uart_write,
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- .endianness = DEVICE_NATIVE_ENDIAN,
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+ .endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4
hw/misc/sifive_e_aon.c
+1
-1
@@ -250,7 +250,7 @@ sifive_e_aon_write(void *opaque, hwaddr addr,
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static const MemoryRegionOps sifive_e_aon_ops = {
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.read = sifive_e_aon_read,
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.write = sifive_e_aon_write,
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- .endianness = DEVICE_NATIVE_ENDIAN,
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+ .endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4
hw/misc/sifive_e_prci.c
+1
-1
@@ -75,7 +75,7 @@ static void sifive_e_prci_write(void *opaque, hwaddr addr,
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static const MemoryRegionOps sifive_e_prci_ops = {
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.read = sifive_e_prci_read,
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.write = sifive_e_prci_write,
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- .endianness = DEVICE_NATIVE_ENDIAN,
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+ .endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4
hw/misc/sifive_u_otp.c
+1
-1
@@ -187,7 +187,7 @@ static void sifive_u_otp_write(void *opaque, hwaddr addr,
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static const MemoryRegionOps sifive_u_otp_ops = {
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.read = sifive_u_otp_read,
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.write = sifive_u_otp_write,
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- .endianness = DEVICE_NATIVE_ENDIAN,
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+ .endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4
hw/misc/sifive_u_prci.c
+1
-1
@@ -112,7 +112,7 @@ static void sifive_u_prci_write(void *opaque, hwaddr addr,
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static const MemoryRegionOps sifive_u_prci_ops = {
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.read = sifive_u_prci_read,
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.write = sifive_u_prci_write,
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- .endianness = DEVICE_NATIVE_ENDIAN,
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+ .endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4
hw/riscv/riscv-iommu.c
+1
-1
@@ -2375,7 +2375,7 @@ static MemTxResult riscv_iommu_mmio_read(void *opaque, hwaddr addr,
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static const MemoryRegionOps riscv_iommu_mmio_ops = {
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.read_with_attrs = riscv_iommu_mmio_read,
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.write_with_attrs = riscv_iommu_mmio_write,
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- .endianness = DEVICE_NATIVE_ENDIAN,
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+ .endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 8,
hw/sd/cadence_sdhci.c
+1
-1
@@ -122,7 +122,7 @@ static void cadence_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
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static const MemoryRegionOps cadence_sdhci_ops = {
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.read = cadence_sdhci_read,
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.write = cadence_sdhci_write,
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- .endianness = DEVICE_NATIVE_ENDIAN,
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+ .endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
hw/timer/ibex_timer.c
+1
-1
@@ -234,7 +234,7 @@ static void ibex_timer_write(void *opaque, hwaddr addr,
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static const MemoryRegionOps ibex_timer_ops = {
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.read = ibex_timer_read,
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.write = ibex_timer_write,
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- .endianness = DEVICE_NATIVE_ENDIAN,
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+ .endianness = DEVICE_LITTLE_ENDIAN,
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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};
hw/timer/sifive_pwm.c
+1
-1
@@ -388,7 +388,7 @@ static void sifive_pwm_reset(DeviceState *dev)
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static const MemoryRegionOps sifive_pwm_ops = {
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.read = sifive_pwm_read,
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.write = sifive_pwm_write,
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- .endianness = DEVICE_NATIVE_ENDIAN,
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+ .endianness = DEVICE_LITTLE_ENDIAN,
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};
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static const VMStateDescription vmstate_sifive_pwm = {