ppc/pnv: Remove Power8E and Power8NVL pnv chips
Power8E and Power8NVL were deprecated since QEMU 10.1, with commit 264a604e7163 ("target/ppc: Deprecate Power8E and Power8NVL") Accordingly, remove usage of 8E and 8NVL chips from powernv, as it's old and unmaintained now. Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Tested-by: Misbah Anjum N <misanjum@linux.ibm.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260703085955.2318600-7-adityag@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Aditya Gupta committed
Jul 3, 2026 at 14:29 UTC
cfa89bd78ad36123f99430ec8484714382c9efbf
5 files changed
+1
-82
docs/system/ppc/powernv.rst
+1
-1
@@ -15,7 +15,7 @@ beyond the scope of what QEMU addresses today.
15
Supported devices
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-----------------
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- * Multi processor support for POWER8, POWER8NVL, POWER9, Power10 and Power11.
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+ * Multi processor support for POWER8, POWER9, Power10 and Power11.
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* XSCOM, serial communication sideband bus to configure chiplets.
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* Simple LPC Controller.
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* Processor Service Interface (PSI) Controller.
hw/ppc/pnv.c
-62
@@ -869,16 +869,6 @@ static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
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return pnv_lpc_isa_create(&chip8->lpc, true, errp);
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}
871
872
-static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
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-{
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- Pnv8Chip *chip8 = PNV8_CHIP(chip);
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- qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C);
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-
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- qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq);
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-
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- return pnv_lpc_isa_create(&chip8->lpc, false, errp);
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-}
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-
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static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
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{
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Pnv9Chip *chip9 = PNV9_CHIP(chip);
@@ -1646,7 +1636,6 @@ static void *pnv_chip_power11_intc_get(PnvChip *chip)
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* EX14
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* <EX15 reserved>
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*/
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-#define POWER8E_CORE_MASK (0x7070ull)
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#define POWER8_CORE_MASK (0x7e7eull)
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/*
@@ -1827,30 +1816,6 @@ static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
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return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
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}
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-static void pnv_chip_power8e_class_init(ObjectClass *klass, const void *data)
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-{
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- DeviceClass *dc = DEVICE_CLASS(klass);
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- PnvChipClass *k = PNV_CHIP_CLASS(klass);
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-
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- k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
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- k->cores_mask = POWER8E_CORE_MASK;
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- k->num_phbs = 3;
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- k->get_pir_tir = pnv_get_pir_tir_p8;
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- k->intc_create = pnv_chip_power8_intc_create;
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- k->intc_reset = pnv_chip_power8_intc_reset;
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- k->intc_destroy = pnv_chip_power8_intc_destroy;
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- k->intc_print_info = pnv_chip_power8_intc_print_info;
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- k->isa_create = pnv_chip_power8_isa_create;
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- k->dt_populate = pnv_chip_power8_dt_populate;
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- k->pic_print_info = pnv_chip_power8_pic_print_info;
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- k->xscom_core_base = pnv_chip_power8_xscom_core_base;
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- k->xscom_pcba = pnv_chip_power8_xscom_pcba;
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- dc->desc = "PowerNV Chip POWER8E";
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-
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- device_class_set_parent_realize(dc, pnv_chip_power8_realize,
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- &k->parent_realize);
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-}
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-
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static void pnv_chip_power8_class_init(ObjectClass *klass, const void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
@@ -1875,30 +1840,6 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, const void *data)
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&k->parent_realize);
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}
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-static void pnv_chip_power8nvl_class_init(ObjectClass *klass, const void *data)
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-{
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- DeviceClass *dc = DEVICE_CLASS(klass);
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- PnvChipClass *k = PNV_CHIP_CLASS(klass);
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-
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- k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
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- k->cores_mask = POWER8_CORE_MASK;
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- k->num_phbs = 4;
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- k->get_pir_tir = pnv_get_pir_tir_p8;
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- k->intc_create = pnv_chip_power8_intc_create;
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- k->intc_reset = pnv_chip_power8_intc_reset;
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- k->intc_destroy = pnv_chip_power8_intc_destroy;
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- k->intc_print_info = pnv_chip_power8_intc_print_info;
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- k->isa_create = pnv_chip_power8nvl_isa_create;
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- k->dt_populate = pnv_chip_power8_dt_populate;
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- k->pic_print_info = pnv_chip_power8_pic_print_info;
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- k->xscom_core_base = pnv_chip_power8_xscom_core_base;
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- k->xscom_pcba = pnv_chip_power8_xscom_pcba;
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- dc->desc = "PowerNV Chip POWER8NVL";
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-
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- device_class_set_parent_realize(dc, pnv_chip_power8_realize,
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- &k->parent_realize);
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-}
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-
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static void pnv_chip_power9_instance_init(Object *obj)
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{
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PnvChip *chip = PNV_CHIP(obj);
@@ -3785,9 +3726,6 @@ static const TypeInfo types[] = {
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.instance_size = sizeof(Pnv8Chip),
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},
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DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
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- DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
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- DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
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- pnv_chip_power8nvl_class_init),
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};
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DEFINE_TYPES(types)
hw/ppc/pnv_core.c
-2
@@ -515,9 +515,7 @@ static const TypeInfo pnv_core_infos[] = {
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.class_init = pnv_core_class_init,
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.abstract = true,
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},
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- DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"),
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DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"),
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- DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
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DEFINE_PNV_CORE_TYPE(power9, "power9_v2.2"),
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DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"),
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DEFINE_PNV_CORE_TYPE(power11, "power11_v2.0"),
include/hw/ppc/pnv.h
-8
@@ -39,18 +39,10 @@ typedef struct Pnv10Chip Pnv11Chip;
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#define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
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#define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
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-#define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1")
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-DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8E,
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- TYPE_PNV_CHIP_POWER8E)
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-
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#define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0")
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DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8,
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TYPE_PNV_CHIP_POWER8)
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-#define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0")
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-DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL,
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- TYPE_PNV_CHIP_POWER8NVL)
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-
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#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.2")
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DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9,
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TYPE_PNV_CHIP_POWER9)
tests/qtest/pnv-xscom.h
-9
@@ -12,9 +12,7 @@
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#define SMT 4 /* some tests will break if less than 4 */
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typedef enum PnvChipType {
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- PNV_CHIP_POWER8E, /* AKA Murano (default) */
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PNV_CHIP_POWER8, /* AKA Venice */
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- PNV_CHIP_POWER8NVL, /* AKA Naples */
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PNV_CHIP_POWER9, /* AKA Nimbus */
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PNV_CHIP_POWER10,
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PNV_CHIP_POWER11,
@@ -37,13 +35,6 @@ static const PnvChip pnv_chips[] = {
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.cfam_id = 0x220ea04980000000ull,
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.first_core = 0x1,
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.num_i2c = 0,
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- }, {
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- .chip_type = PNV_CHIP_POWER8NVL,
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- .cpu_model = "POWER8NVL",
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- .xscom_base = 0x0003fc0000000000ull,
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- .cfam_id = 0x120d304980000000ull,
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- .first_core = 0x1,
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- .num_i2c = 0,
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},
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{
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.chip_type = PNV_CHIP_POWER9,