target/riscv: Move CSR declarations to separate csr.h header
Most of these definitions save riscv_csrr, riscv_csrrw, riscv_csr_read, riscv_csr_write are only used in target/. Move declarations to a separate headers which will soon be made internal to target/. csr.h is temporarily included from cpu.h to not break includes from outside target/, this include will be removed in the following commit. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260520125406.28693-24-anjo@rev.ng> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anton Johansson committed
May 20, 2026 at 14:54 UTC
cfc1d1ade17c598999e5bd1283e6c0fa9e5fe7b5
11 files changed
+113
-86
target/riscv/cpu.c
+1
@@ -23,6 +23,7 @@
23
#include "qemu/log.h"
24
#include "cpu.h"
25
#include "cpu_vendorid.h"
26
+#include "target/riscv/csr.h"
27
#include "internals.h"
28
#include "qapi/error.h"
29
#include "qapi/visitor.h"
target/riscv/cpu.h
+1
-86
@@ -905,75 +905,7 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env);
905
RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env);
906
uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm);
907
908
-RISCVException riscv_csrr(CPURISCVState *env, int csrno,
909
- target_ulong *ret_value);
910
-
911
-RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
912
- target_ulong *ret_value, target_ulong new_value,
913
- target_ulong write_mask, uintptr_t ra);
914
-RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
915
- target_ulong *ret_value,
916
- target_ulong new_value,
917
- target_ulong write_mask);
918
-
919
-static inline void riscv_csr_write(CPURISCVState *env, int csrno,
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- target_ulong val)
921
-{
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- riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0);
923
-}
924
-
925
-static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
926
-{
927
- target_ulong val = 0;
928
- riscv_csrr(env, csrno, &val);
929
- return val;
930
-}
931
-
932
-typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
933
- int csrno);
934
-typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
935
- target_ulong *ret_value);
936
-typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
937
- target_ulong new_value,
938
- uintptr_t ra);
939
-typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
940
- target_ulong *ret_value,
941
- target_ulong new_value,
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- target_ulong write_mask);
943
-
944
-RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
945
- Int128 *ret_value);
946
-RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
947
- Int128 *ret_value, Int128 new_value,
948
- Int128 write_mask, uintptr_t ra);
949
-
950
-typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno,
951
- Int128 *ret_value);
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-typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno,
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- Int128 new_value);
954
-
955
-typedef struct {
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- const char *name;
957
- riscv_csr_predicate_fn predicate;
958
- riscv_csr_read_fn read;
959
- riscv_csr_write_fn write;
960
- riscv_csr_op_fn op;
961
- riscv_csr_read128_fn read128;
962
- riscv_csr_write128_fn write128;
963
- /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */
964
- uint32_t min_priv_ver;
965
-} riscv_csr_operations;
966
-
967
-struct RISCVCSR {
968
- int csrno;
969
- bool (*insertion_test)(RISCVCPU *cpu);
970
- riscv_csr_operations csr_ops;
971
-};
972
-
973
-/* CSR function table constants */
974
-enum {
975
- CSR_TABLE_SIZE = 0x1000
976
-};
908
+#include "target/riscv/csr.h"
909
910
/*
911
* The event id are encoded based on the encoding specified in the
@@ -1007,28 +939,11 @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
939
void riscv_add_satp_mode_properties(Object *obj);
940
bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu);
941
1010
-/* CSR function table */
1011
-extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
1012
-bool riscv_csr_is_fpu(int csrno);
1013
-bool riscv_csr_is_vpu(int csrno);
1014
-
942
extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[];
943
1017
-void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
1018
-void riscv_set_csr_ops(int csrno, const riscv_csr_operations *ops);
1019
-
944
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
945
1022
-target_ulong riscv_new_csr_seed(target_ulong new_value,
1023
- target_ulong write_mask);
1024
-
946
const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
947
1027
-/* In th_csr.c */
1028
-extern const RISCVCSR th_csr_list[];
1029
-
1030
-/* Implemented in mips_csr.c */
1031
-extern const RISCVCSR mips_csr_list[];
1032
-
948
const char *priv_spec_to_str(int priv_version);
949
#endif /* RISCV_CPU_H */
target/riscv/csr.c
+1
@@ -21,6 +21,7 @@
21
#include "qemu/log.h"
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#include "qemu/timer.h"
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#include "cpu.h"
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+#include "target/riscv/csr.h"
25
#include "tcg/tcg-cpu.h"
26
#include "pmu.h"
27
#include "time_helper.h"
target/riscv/csr.h
new
+103
@@ -0,0 +1,103 @@
1
+/*
2
+ * QEMU RISC-V CSRs
3
+ *
4
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5
+ * Copyright (c) 2017-2018 SiFive, Inc.
6
+ * SPDX-License-Identifier: GPL-2.0-or-later
7
+ */
8
+
9
+#ifndef RISCV_CSR_H
10
+#define RISCV_CSR_H
11
+
12
+#include "exec/target_long.h"
13
+#include "cpu_bits.h"
14
+
15
+target_ulong riscv_new_csr_seed(target_ulong new_value,
16
+ target_ulong write_mask);
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+
18
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
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+ target_ulong *ret_value);
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+
21
+RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
22
+ target_ulong *ret_value, target_ulong new_value,
23
+ target_ulong write_mask, uintptr_t ra);
24
+RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
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+ target_ulong *ret_value,
26
+ target_ulong new_value,
27
+ target_ulong write_mask);
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+
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+static inline void riscv_csr_write(CPURISCVState *env, int csrno,
30
+ target_ulong val)
31
+{
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+ riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0);
33
+}
34
+
35
+static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
36
+{
37
+ target_ulong val = 0;
38
+ riscv_csrr(env, csrno, &val);
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+ return val;
40
+}
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+
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+typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
43
+ int csrno);
44
+typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
45
+ target_ulong *ret_value);
46
+typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
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+ target_ulong new_value,
48
+ uintptr_t ra);
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+typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
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+ target_ulong *ret_value,
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+ target_ulong new_value,
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+ target_ulong write_mask);
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+
54
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
55
+ Int128 *ret_value);
56
+RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
57
+ Int128 *ret_value, Int128 new_value,
58
+ Int128 write_mask, uintptr_t ra);
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+
60
+typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno,
61
+ Int128 *ret_value);
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+typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno,
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+ Int128 new_value);
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+
65
+typedef struct {
66
+ const char *name;
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+ riscv_csr_predicate_fn predicate;
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+ riscv_csr_read_fn read;
69
+ riscv_csr_write_fn write;
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+ riscv_csr_op_fn op;
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+ riscv_csr_read128_fn read128;
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+ riscv_csr_write128_fn write128;
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+ /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */
74
+ uint32_t min_priv_ver;
75
+} riscv_csr_operations;
76
+
77
+struct RISCVCSR {
78
+ int csrno;
79
+ bool (*insertion_test)(RISCVCPU *cpu);
80
+ riscv_csr_operations csr_ops;
81
+};
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+
83
+/* CSR function table constants */
84
+enum {
85
+ CSR_TABLE_SIZE = 0x1000
86
+};
87
+
88
+/* CSR function table */
89
+extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
90
+
91
+bool riscv_csr_is_fpu(int csrno);
92
+bool riscv_csr_is_vpu(int csrno);
93
+
94
+void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
95
+void riscv_set_csr_ops(int csrno, const riscv_csr_operations *ops);
96
+
97
+/* In th_csr.c */
98
+extern const RISCVCSR th_csr_list[];
99
+
100
+/* Implemented in mips_csr.c */
101
+extern const RISCVCSR mips_csr_list[];
102
+
103
+#endif /* RISCV_CSR_H */
target/riscv/gdbstub.c
+1
@@ -21,6 +21,7 @@
21
#include "gdbstub/helpers.h"
22
#include "cpu.h"
23
#include "internals.h"
24
+#include "target/riscv/csr.h"
25
26
struct TypeSize {
27
const char *gdb_type;
target/riscv/kvm/kvm-cpu.c
+1
@@ -31,6 +31,7 @@
31
#include "system/kvm.h"
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#include "system/kvm_int.h"
33
#include "cpu.h"
34
+#include "target/riscv/csr.h"
35
#include "trace.h"
36
#include "accel/accel-cpu-target.h"
37
#include "hw/pci/pci.h"
target/riscv/mips_csr.c
+1
@@ -10,6 +10,7 @@
10
#include "qemu/osdep.h"
11
#include "cpu.h"
12
#include "cpu_vendorid.h"
13
+#include "target/riscv/csr.h"
14
15
/* Static MIPS CSR state storage */
16
static struct {
target/riscv/monitor.c
+1
@@ -22,6 +22,7 @@
22
#include "qemu/ctype.h"
23
#include "qemu/qemu-print.h"
24
#include "cpu.h"
25
+#include "target/riscv/csr.h"
26
#include "cpu_bits.h"
27
#include "monitor/monitor.h"
28
#include "monitor/hmp.h"
target/riscv/op_helper.c
+1
@@ -20,6 +20,7 @@
20
21
#include "qemu/osdep.h"
22
#include "cpu.h"
23
+#include "target/riscv/csr.h"
24
#include "internals.h"
25
#include "exec/cputlb.h"
26
#include "accel/tcg/cpu-ldst.h"
target/riscv/riscv-qmp-cmds.c
+1
@@ -35,6 +35,7 @@
35
#include "system/tcg.h"
36
#include "cpu-qom.h"
37
#include "cpu.h"
38
+#include "target/riscv/csr.h"
39
40
static void riscv_cpu_add_definition(gpointer data, gpointer user_data)
41
{
target/riscv/th_csr.c
+1
@@ -19,6 +19,7 @@
19
#include "qemu/osdep.h"
20
#include "cpu.h"
21
#include "cpu_vendorid.h"
22
+#include "target/riscv/csr.h"
23
24
#define CSR_TH_SXSTATUS 0x5c0
25