MAINTAINERS: Fix RISCV related paths
Host user-emulation headers were renamed in commits ba0e7333620 ("configure: Merge riscv32 and riscv64 host architectures") and bbf15aaf7c7 ("common-user: Move safe-syscall.* from linux-user"), then covered in commit 355cdac7d86 ("MAINTAINERS: Add common-user/host/riscv to RISC-V section"). Remove the obsolete entries. test_riscv64_sifive_u.py was renamed in commit e1a8572a8d7 ("tests/functional: Move riscv32/riscv64 tests into target-specific folders"). Reported-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20260519172621.98469-1-philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Philippe Mathieu-Daudé committed
May 19, 2026 at 19:26 UTC
d239c1d7b965c7ab1a6a8210c5aa9b9f038fbb43
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MAINTAINERS
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@@ -362,8 +362,6 @@ F: hw/riscv/
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F: hw/intc/riscv*
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F: include/hw/char/riscv_htif.h
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F: include/hw/riscv/
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-F: linux-user/host/riscv32/
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-F: linux-user/host/riscv64/
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F: common-user/host/riscv*
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F: tests/functional/riscv32
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F: tests/functional/riscv64
@@ -1782,7 +1780,7 @@ S: Supported
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F: docs/system/riscv/sifive_u.rst
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F: hw/*/*sifive*.c
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F: include/hw/*/*sifive*.h
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-F: tests/functional/test_riscv64_sifive_u.py
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+F: tests/functional/riscv64/test_sifive_u.py
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AMD Microblaze-V Generic Board
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M: Sai Pavan Boddu <sai.pavan.boddu@amd.com>