target/arm/tcg/translate.c: extract aarch64_translate_code()
This allows to get rid of TARGET_AARCH64, and helps with next patch which will define at runtime tcg address type, by adding a second entry point in a different source file. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20260407222208.271838-14-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Pierrick Bouvier committed
Apr 23, 2026 at 10:24 UTC
d41238625eed96fbe07aa0fba566775b3f6aa7e4
4 files changed
+27
-10
target/arm/internals.h
+2
@@ -381,6 +381,8 @@ void arm_init_cpreg_list(ARMCPU *cpu);
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void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
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void arm_translate_init(void);
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+void aarch64_translate_code(CPUState *cs, TranslationBlock *tb,
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+ int *max_insns, vaddr pc, void *host_pc);
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void arm_translate_code(CPUState *cs, TranslationBlock *tb,
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int *max_insns, vaddr pc, void *host_pc);
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target/arm/tcg/stubs32.c
+7
@@ -3,6 +3,7 @@
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*/
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#include "qemu/osdep.h"
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+#include "target/arm/internals.h"
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#include "target/arm/tcg/translate.h"
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@@ -15,3 +16,9 @@ void a64_translate_init(void)
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{
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/* Don't initialize for 32 bits. Call site will be fixed later. */
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}
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+
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+void aarch64_translate_code(CPUState *cs, TranslationBlock *tb,
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+ int *max_insns, vaddr pc, void *host_pc)
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+{
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+ g_assert_not_reached();
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+}
target/arm/tcg/translate-a64.c
+9
@@ -18,6 +18,7 @@
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*/
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#include "qemu/osdep.h"
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#include "exec/target_page.h"
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+#include "exec/translator.h"
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#include "helper-a64.h"
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#include "helper-sme.h"
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#include "helper-sve.h"
@@ -10949,3 +10950,11 @@ const TranslatorOps aarch64_translator_ops = {
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.translate_insn = aarch64_tr_translate_insn,
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.tb_stop = aarch64_tr_tb_stop,
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};
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+
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+void aarch64_translate_code(CPUState *cpu, TranslationBlock *tb,
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+ int *max_insns, vaddr pc, void *host_pc)
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+{
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+ DisasContext dc = {};
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+ translator_loop(cpu, tb, max_insns, pc, host_pc,
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+ &aarch64_translator_ops, &dc.base);
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+}
target/arm/tcg/translate.c
+9
-10
@@ -28,6 +28,7 @@
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#include "semihosting/semihost.h"
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#include "cpregs.h"
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#include "exec/target_page.h"
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+#include "exec/translator.h"
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#include "helper.h"
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#include "helper-mve.h"
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@@ -6878,18 +6879,16 @@ static const TranslatorOps thumb_translator_ops = {
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void arm_translate_code(CPUState *cpu, TranslationBlock *tb,
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int *max_insns, vaddr pc, void *host_pc)
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{
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- DisasContext dc = { };
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- const TranslatorOps *ops = &arm_translator_ops;
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CPUARMTBFlags tb_flags = arm_tbflags_from_tb(tb);
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- if (EX_TBFLAG_AM32(tb_flags, THUMB)) {
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- ops = &thumb_translator_ops;
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- }
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-#ifdef TARGET_AARCH64
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if (EX_TBFLAG_ANY(tb_flags, AARCH64_STATE)) {
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- ops = &aarch64_translator_ops;
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+ aarch64_translate_code(cpu, tb, max_insns, pc, host_pc);
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+ } else {
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+ DisasContext dc = { };
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+ translator_loop(cpu, tb, max_insns, pc, host_pc,
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+ (EX_TBFLAG_AM32(tb_flags, THUMB)
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+ ? &thumb_translator_ops
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+ : &arm_translator_ops),
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+ &dc.base);
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}
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-#endif
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-
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- translator_loop(cpu, tb, max_insns, pc, host_pc, ops, &dc.base);
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}