@samitouri / QOSamiQemu / commits / d45b9bc655

target/riscv: move TCG only files to tcg subdir

We have *way* too much TCG-only code hanging around in target/riscv, where ideally we would have things that are shared between accelerators. We'll follow the example of other targets like i386 and loongarch and move everything to the tcg subir. This will not only cleanup target/riscv but it will also expose what is common code but it's buried inside a TCG helper. We're leaving some stuff behind because these require a little more case to not end up breaking KVM. We'll take care of them next. Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com> Message-ID: <20260703180538.3346781-5-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Daniel Henrique Barboza committed Jul 3, 2026 at 15:05 UTC d45b9bc65515e376f360cc8c2877cc94f22d4e49
50 files changed +28 -18
target/riscv/meson.build
-16
@@ -16,31 +16,15 @@ riscv_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING',
16
17 riscv_ss.add(files(
18 'cpu.c',
19 - 'cpu_helper.c',
20 - 'csr.c',
21 - 'fpu_helper.c',
19 'gdbstub.c',
23 - 'op_helper.c',
24 - 'vector_helper.c',
25 - 'vector_internals.c',
26 - 'bitmanip_helper.c',
27 - 'translate.c',
28 - 'm128_helper.c',
29 - 'crypto_helper.c',
30 - 'zce_helper.c',
31 - 'vcrypto_helper.c'
20 ))
21
22 riscv_system_ss = ss.source_set()
23 riscv_system_ss.add(files(
24 'arch_dump.c',
25 'pmp.c',
38 - 'debug.c',
26 'monitor.c',
27 'machine.c',
41 - 'mips_csr.c',
42 - 'pmu.c',
43 - 'th_csr.c',
28 'time_helper.c',
29 'riscv-qmp-cmds.c',
30 ))
target/riscv/tcg/bitmanip_helper.c renamed
target/riscv/tcg/cpu_helper.c renamed
target/riscv/tcg/crypto_helper.c renamed
target/riscv/tcg/csr.c renamed
target/riscv/tcg/debug.c renamed
target/riscv/tcg/fpu_helper.c renamed
target/riscv/tcg/insn_trans/trans_privileged.c.inc renamed
target/riscv/tcg/insn_trans/trans_rva.c.inc renamed
target/riscv/tcg/insn_trans/trans_rvb.c.inc renamed
target/riscv/tcg/insn_trans/trans_rvbf16.c.inc renamed
target/riscv/tcg/insn_trans/trans_rvd.c.inc renamed
target/riscv/tcg/insn_trans/trans_rvf.c.inc renamed
target/riscv/tcg/insn_trans/trans_rvh.c.inc renamed
target/riscv/tcg/insn_trans/trans_rvi.c.inc renamed
target/riscv/tcg/insn_trans/trans_rvk.c.inc renamed
target/riscv/tcg/insn_trans/trans_rvm.c.inc renamed
target/riscv/tcg/insn_trans/trans_rvv.c.inc renamed
target/riscv/tcg/insn_trans/trans_rvvk.c.inc renamed
target/riscv/tcg/insn_trans/trans_rvzabha.c.inc renamed
target/riscv/tcg/insn_trans/trans_rvzacas.c.inc renamed
target/riscv/tcg/insn_trans/trans_rvzalasr.c.inc renamed
target/riscv/tcg/insn_trans/trans_rvzawrs.c.inc renamed
target/riscv/tcg/insn_trans/trans_rvzce.c.inc renamed
target/riscv/tcg/insn_trans/trans_rvzcmop.c.inc renamed
target/riscv/tcg/insn_trans/trans_rvzfa.c.inc renamed
target/riscv/tcg/insn_trans/trans_rvzfh.c.inc renamed
target/riscv/tcg/insn_trans/trans_rvzicbo.c.inc renamed
target/riscv/tcg/insn_trans/trans_rvzicfiss.c.inc renamed
target/riscv/tcg/insn_trans/trans_rvzicond.c.inc renamed
target/riscv/tcg/insn_trans/trans_rvzimop.c.inc renamed
target/riscv/tcg/insn_trans/trans_svinval.c.inc renamed
target/riscv/tcg/insn_trans/trans_xlrbr.c.inc renamed
target/riscv/tcg/insn_trans/trans_xmips.c.inc renamed
target/riscv/tcg/insn_trans/trans_xthead.c.inc renamed
target/riscv/tcg/insn_trans/trans_xventanacondops.c.inc renamed
target/riscv/tcg/insn_trans/trans_zilsd.c.inc renamed
target/riscv/tcg/m128_helper.c renamed
target/riscv/tcg/meson.build
+28 -2
@@ -1,2 +1,28 @@
1 -riscv_ss.add(when: 'CONFIG_TCG', if_true: files(
2 - 'tcg-cpu.c'))
1 +if 'CONFIG_TCG' not in config_all_accel
2 + subdir_done()
3 +endif
4 +
5 +riscv_ss.add(files(
6 + 'bitmanip_helper.c',
7 + 'cpu_helper.c',
8 + 'csr.c',
9 + 'crypto_helper.c',
10 + 'fpu_helper.c',
11 + 'm128_helper.c',
12 + 'op_helper.c',
13 + 'translate.c',
14 + 'tcg-cpu.c',
15 + 'vcrypto_helper.c',
16 + 'vector_helper.c',
17 + 'vector_internals.c',
18 + 'zce_helper.c'))
19 +
20 +
21 +riscv_system_ss.add(files(
22 + 'debug.c',
23 + 'mips_csr.c',
24 + 'pmu.c',
25 + 'th_csr.c',
26 +))
27 +
28 +
target/riscv/tcg/mips_csr.c renamed
target/riscv/tcg/op_helper.c renamed
target/riscv/tcg/pmu.c renamed
target/riscv/tcg/pmu.h renamed
target/riscv/tcg/th_csr.c renamed
target/riscv/tcg/translate.c renamed
target/riscv/tcg/vcrypto_helper.c renamed
target/riscv/tcg/vector_helper.c renamed
target/riscv/tcg/vector_internals.c renamed
target/riscv/tcg/vector_internals.h renamed
target/riscv/tcg/zce_helper.c renamed