target/hexagon: Define register fields for system regs
Define the register fields for ssr, schedcfg, stid, bestwait, ccr, modectl, imask, ipendad. Define the fields for TLB entries. Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Brian Cain committed
Jun 22, 2026 at 15:28 UTC
d46a98747e352aac53a5c99c093c5a388a037a4a
1 file changed
+96
target/hexagon/reg_fields_def.h.inc
+96
@@ -39,3 +39,99 @@ DEF_REG_FIELD(USR_FPDBZE, 26, 1)
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DEF_REG_FIELD(USR_FPOVFE, 27, 1)
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DEF_REG_FIELD(USR_FPUNFE, 28, 1)
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DEF_REG_FIELD(USR_FPINPE, 29, 1)
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+
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+DEF_REG_FIELD(IPENDAD_IAD, 16, 16)
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+DEF_REG_FIELD(IPENDAD_IPEND, 0, 16)
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+
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+DEF_REG_FIELD(SCHEDCFG_EN, 8, 1)
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+DEF_REG_FIELD(SCHEDCFG_INTNO, 0, 4)
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+DEF_REG_FIELD(BESTWAIT_PRIO, 0, 9)
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+
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+
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+/* PTE (aka TLB entry) fields */
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+DEF_REG_FIELD(PTE_PPD, 0, 24)
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+DEF_REG_FIELD(PTE_C, 24, 4)
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+DEF_REG_FIELD(PTE_U, 28, 1)
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+DEF_REG_FIELD(PTE_R, 29, 1)
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+DEF_REG_FIELD(PTE_W, 30, 1)
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+DEF_REG_FIELD(PTE_X, 31, 1)
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+DEF_REG_FIELD(PTE_VPN, 32, 20)
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+DEF_REG_FIELD(PTE_ASID, 52, 7)
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+DEF_REG_FIELD(PTE_ATR0, 59, 1)
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+DEF_REG_FIELD(PTE_ATR1, 60, 1)
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+DEF_REG_FIELD(PTE_PA35, 61, 1)
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+DEF_REG_FIELD(PTE_G, 62, 1)
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+DEF_REG_FIELD(PTE_V, 63, 1)
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+
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+/* SYSCFG fields */
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+DEF_REG_FIELD(SYSCFG_MMUEN, 0, 1)
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+DEF_REG_FIELD(SYSCFG_ICEN, 1, 1)
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+DEF_REG_FIELD(SYSCFG_DCEN, 2, 1)
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+DEF_REG_FIELD(SYSCFG_ISDBTRUSTED, 3, 1)
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+DEF_REG_FIELD(SYSCFG_GIE, 4, 1)
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+DEF_REG_FIELD(SYSCFG_ISDBREADY, 5, 1)
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+DEF_REG_FIELD(SYSCFG_PCYCLEEN, 6, 1)
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+DEF_REG_FIELD(SYSCFG_V2X, 7, 1)
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+DEF_REG_FIELD(SYSCFG_IGNOREDABORT, 8, 1)
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+DEF_REG_FIELD(SYSCFG_PM, 9, 1)
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+DEF_REG_FIELD(SYSCFG_TLBLOCK, 11, 1)
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+DEF_REG_FIELD(SYSCFG_K0LOCK, 12, 1)
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+DEF_REG_FIELD(SYSCFG_BQ, 13, 1)
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+DEF_REG_FIELD(SYSCFG_PRIO, 14, 1)
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+DEF_REG_FIELD(SYSCFG_DMT, 15, 1)
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+DEF_REG_FIELD(SYSCFG_L2CFG, 16, 3)
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+DEF_REG_FIELD(SYSCFG_ITCM, 19, 1)
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+DEF_REG_FIELD(SYSCFG_L2NWA, 21, 1)
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+DEF_REG_FIELD(SYSCFG_L2NRA, 22, 1)
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+DEF_REG_FIELD(SYSCFG_L2WB, 23, 1)
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+DEF_REG_FIELD(SYSCFG_L2P, 24, 1)
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+DEF_REG_FIELD(SYSCFG_SLVCTL0, 25, 2)
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+DEF_REG_FIELD(SYSCFG_SLVCTL1, 27, 2)
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+DEF_REG_FIELD(SYSCFG_L2PARTSIZE, 29, 2)
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+DEF_REG_FIELD(SYSCFG_L2GCA, 31, 1)
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+
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+/* SSR fields */
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+DEF_REG_FIELD(SSR_CAUSE, 0, 8)
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+DEF_REG_FIELD(SSR_ASID, 8, 7)
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+DEF_REG_FIELD(SSR_UM, 16, 1)
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+DEF_REG_FIELD(SSR_EX, 17, 1)
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+DEF_REG_FIELD(SSR_IE, 18, 1)
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+DEF_REG_FIELD(SSR_GM, 19, 1)
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+DEF_REG_FIELD(SSR_V0, 20, 1)
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+DEF_REG_FIELD(SSR_V1, 21, 1)
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+DEF_REG_FIELD(SSR_BVS, 22, 1)
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+DEF_REG_FIELD(SSR_CE, 23, 1)
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+DEF_REG_FIELD(SSR_PE, 24, 1)
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+DEF_REG_FIELD(SSR_BP, 25, 1)
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+DEF_REG_FIELD(SSR_XE2, 26, 1)
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+DEF_REG_FIELD(SSR_XA, 27, 3)
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+DEF_REG_FIELD(SSR_SS, 30, 1)
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+DEF_REG_FIELD(SSR_XE, 31, 1)
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+
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+/* misc registers */
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+DEF_REG_FIELD(IMASK_MASK, 0, 16)
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+
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+DEF_REG_FIELD(STID_PRIO, 16, 8)
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+DEF_REG_FIELD(STID_STID, 0, 8)
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+
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+/* MODECTL fields */
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+DEF_REG_FIELD(MODECTL_E, 0, 8)
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+DEF_REG_FIELD(MODECTL_W, 16, 8)
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+
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+DEF_REG_FIELD(CCR_L1ICP, 0, 2)
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+DEF_REG_FIELD(CCR_L1DCP, 3, 2)
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+DEF_REG_FIELD(CCR_L2CP, 6, 2)
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+
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+DEF_REG_FIELD(CCR_HFI, 16, 1)
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+DEF_REG_FIELD(CCR_HFD, 17, 1)
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+DEF_REG_FIELD(CCR_HFIL2, 18, 1)
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+DEF_REG_FIELD(CCR_HFDL2, 19, 1)
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+DEF_REG_FIELD(CCR_SFD, 20, 1)
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+
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+DEF_REG_FIELD(CCR_GIE, 24, 1)
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+DEF_REG_FIELD(CCR_GTE, 25, 1)
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+DEF_REG_FIELD(CCR_GEE, 26, 1)
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+DEF_REG_FIELD(CCR_GRE, 27, 1)
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+DEF_REG_FIELD(CCR_VV1, 29, 1)
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+DEF_REG_FIELD(CCR_VV2, 30, 1)
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+DEF_REG_FIELD(CCR_VV3, 31, 1)