target/arm: Extract common code related to 'max' CPU
Extract common code related to 'max' CPU. This commit only move code used by the 32-bit 'max' CPU, but we will soon add the 64-bit counterpart, so name it generically as "cpu-max.c". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20260526203722.79463-10-philmd@linaro.org>
Philippe Mathieu-Daudé committed
Apr 8, 2026 at 15:30 UTC
d4b14960f6a593e79d92d53011d970c4a598c4ce
3 files changed
+107
-96
target/arm/cpu-max.c
new
+106
@@ -0,0 +1,106 @@
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+/*
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+ * QEMU ARM 'max' CPU
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+ *
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+ * Copyright (c) 2018 Linaro Ltd
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+ *
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#include "qemu/osdep.h"
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+#include "target/arm/internals.h"
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+
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+/* Share AArch32 -cpu max features with AArch64. */
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+void aa32_max_features(ARMCPU *cpu)
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+{
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+ uint32_t t;
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+ ARMISARegisters *isar = &cpu->isar;
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+
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+ /* Add additional features supported by QEMU */
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+ t = GET_IDREG(isar, ID_ISAR5);
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+ t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
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+ t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
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+ t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
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+ t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
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+ t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
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+ t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
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+ SET_IDREG(isar, ID_ISAR5, t);
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+
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+ t = GET_IDREG(isar, ID_ISAR6);
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+ t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
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+ t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
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+ t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
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+ t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */
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+ t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
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+ t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
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+ t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
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+ SET_IDREG(isar, ID_ISAR6, t);
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+
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+ t = cpu->isar.mvfr1;
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+ t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
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+ t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */
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+ cpu->isar.mvfr1 = t;
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+
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+ t = cpu->isar.mvfr2;
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+ t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
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+ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
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+ cpu->isar.mvfr2 = t;
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+
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+ FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
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+
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+ t = GET_IDREG(isar, ID_MMFR4);
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+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */
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+ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
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+ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
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+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
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+ t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */
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+ SET_IDREG(isar, ID_MMFR4, t);
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+
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+ FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */
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+
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+ t = GET_IDREG(isar, ID_PFR0);
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+ t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */
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+ t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
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+ t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
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+ SET_IDREG(isar, ID_PFR0, t);
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+
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+ t = GET_IDREG(isar, ID_PFR2);
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+ t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
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+ t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
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+ SET_IDREG(isar, ID_PFR2, t);
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+
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+ t = GET_IDREG(isar, ID_DFR0);
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+ t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */
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+ t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */
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+ t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
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+ SET_IDREG(isar, ID_DFR0, t);
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+
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+ /* Debug ID registers. */
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+
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+ /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */
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+ t = 0x00008000;
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+ t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1);
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+ t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1);
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+ t = FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */
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+ t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1);
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+ t = FIELD_DP32(t, DBGDIDR, BRPS, 5);
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+ t = FIELD_DP32(t, DBGDIDR, WRPS, 3);
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+ cpu->isar.dbgdidr = t;
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+
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+ t = 0;
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+ t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3);
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+ t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1);
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+ t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15);
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+ t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0);
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+ t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1);
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+ t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1);
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+ t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0);
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+ t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0);
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+ cpu->isar.dbgdevid = t;
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+
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+ /* Bits[31:4] are RES0. */
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+ t = 0;
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+ t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2);
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+ cpu->isar.dbgdevid1 = t;
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+
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+ FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */
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+}
target/arm/meson.build
+1
@@ -9,6 +9,7 @@ arm_user_ss = ss.source_set()
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arm_common_system_ss.add(files('gdbstub.c'))
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arm_user_ss.add(files('gdbstub.c'))
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+arm_ss.add(files('cpu-max.c'))
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arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
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'cpu64.c',
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))
target/arm/tcg/cpu32.c
-96
@@ -18,102 +18,6 @@
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#include "cpregs.h"
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-/* Share AArch32 -cpu max features with AArch64. */
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-void aa32_max_features(ARMCPU *cpu)
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-{
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- uint32_t t;
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- ARMISARegisters *isar = &cpu->isar;
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-
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- /* Add additional features supported by QEMU */
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- t = GET_IDREG(isar, ID_ISAR5);
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- t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
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- t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
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- t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
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- t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
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- t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
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- t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
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- SET_IDREG(isar, ID_ISAR5, t);
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-
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- t = GET_IDREG(isar, ID_ISAR6);
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- t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
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- t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
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- t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
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- t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */
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- t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
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- t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
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- t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
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- SET_IDREG(isar, ID_ISAR6, t);
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-
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- t = cpu->isar.mvfr1;
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- t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
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- t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */
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- cpu->isar.mvfr1 = t;
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-
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- t = cpu->isar.mvfr2;
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- t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
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- t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
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- cpu->isar.mvfr2 = t;
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-
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- FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
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-
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- t = GET_IDREG(isar, ID_MMFR4);
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- t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */
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- t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
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- t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
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- t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
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- t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */
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- SET_IDREG(isar, ID_MMFR4, t);
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-
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- FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */
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-
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- t = GET_IDREG(isar, ID_PFR0);
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- t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */
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- t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
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- t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
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- SET_IDREG(isar, ID_PFR0, t);
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-
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- t = GET_IDREG(isar, ID_PFR2);
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- t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
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- t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
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- SET_IDREG(isar, ID_PFR2, t);
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-
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- t = GET_IDREG(isar, ID_DFR0);
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- t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */
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- t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */
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- t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
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- SET_IDREG(isar, ID_DFR0, t);
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-
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- /* Debug ID registers. */
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-
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- /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */
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- t = 0x00008000;
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- t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1);
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- t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1);
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- t = FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */
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- t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1);
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- t = FIELD_DP32(t, DBGDIDR, BRPS, 5);
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- t = FIELD_DP32(t, DBGDIDR, WRPS, 3);
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- cpu->isar.dbgdidr = t;
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-
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- t = 0;
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- t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3);
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- t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1);
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- t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15);
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- t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0);
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- t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1);
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- t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1);
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- t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0);
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- t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0);
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- cpu->isar.dbgdevid = t;
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-
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- /* Bits[31:4] are RES0. */
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- t = 0;
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- t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2);
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- cpu->isar.dbgdevid1 = t;
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-
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- FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */
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-}
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-
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/* CPU models. These are not needed for the AArch64 linux-user build. */
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#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
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