target/riscv: Define MSTATUS_SBE and MSTATUS_MBE bit masks

Add the RISC-V privileged ISA defined bit positions for the Supervisor Big-Endian (SBE, bit 36) and Machine Big-Endian (MBE, bit 37) fields in the mstatus register. These are used alongside the existing MSTATUS_UBE (bit 6) to control data endianness at each privilege level. The MSTATUS_UBE definition was already present, but SBE and MBE were missing. Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260527083151.17876-2-djordje.todorovic@htecgroup.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>