target/ppc: convert slw, srw instruction via decode spec
Move slw and srw to decodetree specification using the @X_rc format. The existing shift-masking logic from gen_slw/gen_srw is preserved verbatim in the new trans_SLW/trans_SRW handlers. Signed-off-by: Mukesh Kumar Chaurasiya (IBM) <mkchauras@gmail.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Tested-by: Aniket Sahu <asahu1x@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-8-rathc@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Mukesh Kumar Chaurasiya (IBM) committed
Aug 27, 2026 at 18:59 UTC
d558d05f600ee8f2c1e28e6b6699e36e9bccb8c0
3 files changed
+53
-49
target/ppc/insn32.decode
+5
@@ -505,6 +505,11 @@ HASHCHK 011111 ..... ..... ..... 1011110010 . @X_DW
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HASHSTP 011111 ..... ..... ..... 1010010010 . @X_DW
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HASHCHKP 011111 ..... ..... ..... 1010110010 . @X_DW
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+# Fixed-Point Shift Instructions
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+
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+SLW 011111 ..... ..... ..... 0000011000 . @X_rc
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+SRW 011111 ..... ..... ..... 1000011000 . @X_rc
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+
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## BCD Assist
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ADDG6S 011111 ..... ..... ..... - 001001010 - @X
target/ppc/translate.c
-49
@@ -2315,29 +2315,6 @@ GEN_PPC64_R4(rldimi, 0x1E, 0x06);
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/*** Integer shift ***/
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-/* slw & slw. */
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-static void gen_slw(DisasContext *ctx)
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-{
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- TCGv t0, t1;
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-
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- t0 = tcg_temp_new();
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- /* AND rS with a mask that is 0 when rB >= 0x20 */
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-#if defined(TARGET_PPC64)
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- tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
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- tcg_gen_sari_tl(t0, t0, 0x3f);
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-#else
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- tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
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- tcg_gen_sari_tl(t0, t0, 0x1f);
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-#endif
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- tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
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- t1 = tcg_temp_new();
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- tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
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- tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
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- tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
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- if (unlikely(Rc(ctx->opcode) != 0)) {
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- gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
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- }
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-}
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/* sraw & sraw. */
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static void gen_sraw(DisasContext *ctx)
@@ -2379,30 +2356,6 @@ static void gen_srawi(DisasContext *ctx)
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}
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}
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-/* srw & srw. */
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-static void gen_srw(DisasContext *ctx)
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-{
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- TCGv t0, t1;
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-
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- t0 = tcg_temp_new();
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- /* AND rS with a mask that is 0 when rB >= 0x20 */
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-#if defined(TARGET_PPC64)
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- tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
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- tcg_gen_sari_tl(t0, t0, 0x3f);
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-#else
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- tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
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- tcg_gen_sari_tl(t0, t0, 0x1f);
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-#endif
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- tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
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- tcg_gen_ext32u_tl(t0, t0);
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- t1 = tcg_temp_new();
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- tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
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- tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
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- if (unlikely(Rc(ctx->opcode) != 0)) {
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- gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
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- }
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-}
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-
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#if defined(TARGET_PPC64)
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/* sld & sld. */
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static void gen_sld(DisasContext *ctx)
@@ -5764,10 +5717,8 @@ GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
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GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
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GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
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GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
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-GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
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GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
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GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
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-GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
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#if defined(TARGET_PPC64)
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GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
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GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
target/ppc/translate/fixedpoint-impl.c.inc
+48
@@ -1406,3 +1406,51 @@ TRANS(HASHST, do_hash, false, gen_helper_HASHST)
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TRANS(HASHCHK, do_hash, false, gen_helper_HASHCHK)
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TRANS(HASHSTP, do_hash, true, gen_helper_HASHSTP)
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TRANS(HASHCHKP, do_hash, true, gen_helper_HASHCHKP)
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+
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+static bool trans_SLW(DisasContext *ctx, arg_SLW *a)
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+{
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+ TCGv t0, t1;
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+
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+ t0 = tcg_temp_new();
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+ /* AND rt with a mask that is 0 when rB >= 0x20 */
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+#if defined(TARGET_PPC64)
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+ tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x3a);
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+ tcg_gen_sari_tl(t0, t0, 0x3f);
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+#else
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+ tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x1a);
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+ tcg_gen_sari_tl(t0, t0, 0x1f);
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+#endif
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+ tcg_gen_andc_tl(t0, cpu_gpr[a->rt], t0);
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+ t1 = tcg_temp_new();
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+ tcg_gen_andi_tl(t1, cpu_gpr[a->rb], 0x1f);
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+ tcg_gen_shl_tl(cpu_gpr[a->ra], t0, t1);
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+ tcg_gen_ext32u_tl(cpu_gpr[a->ra], cpu_gpr[a->ra]);
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+ if (unlikely(a->rc)) {
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+ gen_set_Rc0(ctx, cpu_gpr[a->ra]);
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+ }
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+ return true;
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+}
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+
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+static bool trans_SRW(DisasContext *ctx, arg_SRW *a)
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+{
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+ TCGv t0, t1;
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+
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+ t0 = tcg_temp_new();
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+ /* AND rt with a mask that is 0 when rB >= 0x20 */
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+#if defined(TARGET_PPC64)
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+ tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x3a);
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+ tcg_gen_sari_tl(t0, t0, 0x3f);
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+#else
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+ tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x1a);
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+ tcg_gen_sari_tl(t0, t0, 0x1f);
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+#endif
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+ tcg_gen_andc_tl(t0, cpu_gpr[a->rt], t0);
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+ tcg_gen_ext32u_tl(t0, t0);
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+ t1 = tcg_temp_new();
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+ tcg_gen_andi_tl(t1, cpu_gpr[a->rb], 0x1f);
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+ tcg_gen_shr_tl(cpu_gpr[a->ra], t0, t1);
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+ if (unlikely(a->rc)) {
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+ gen_set_Rc0(ctx, cpu_gpr[a->ra]);
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+ }
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+ return true;
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+}