hw/dma/zynq: Ensure PCFG_DONE bit remains set to indicate PL is in user mode
All register bits are clear on write by writing 1s to those bits, however the register bits will only be cleared if the condition that sets the interrupt flag is no longer true. Since we can assume that programming is always done, the `PCFG_DONE` flag is always set to 1, so it will not never be cleared. Signed-off-by: YannickV <Y.Vossen@beckhoff.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-id: 20260518073401.11279-4-corvin.koehne@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
YannickV committed
May 18, 2026 at 09:33 UTC
d5fb3d22d1818ffbe88bbb92dd32462190e7585e
1 file changed
+2
hw/dma/xlnx-zynq-devcfg.c
+2
@@ -188,6 +188,8 @@ static void r_ixr_post_write(RegisterInfo *reg, uint64_t val)
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{
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XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
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+ s->regs[R_INT_STS] |= R_INT_STS_PCFG_DONE_MASK;
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+
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xlnx_zynq_devcfg_update_ixr(s);
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}
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