disas/riscv: Fix isa decoding of rev8
The encoding of rev8 is different for rv32 and rv64. Cc: qemu-stable@nongnu.org Fixes: 02c1b569a15 ("disas/riscv: Add Zb[abcs] instructions") Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260812223142.349142-40-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Richard Henderson committed
Aug 12, 2026 at 15:31 UTC
d610e55c8390a8bfd15d0a4f1521d7fc46e4e0b7
1 file changed
+10
-2
disas/riscv.c
+10
-2
@@ -3292,8 +3292,16 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
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case 0b01100: op = rv_op_rori; break;
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case 0b01101:
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switch ((inst >> 20) & 0b1111111) {
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- case 0b0011000: op = rv_op_rev8; break;
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- case 0b0111000: op = rv_op_rev8; break;
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+ case 0b0011000:
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+ if (isa == rv32) {
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+ op = rv_op_rev8;
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+ }
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+ break;
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+ case 0b0111000:
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+ if (isa == rv64) {
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+ op = rv_op_rev8;
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+ }
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+ break;
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case 0b0000111: op = rv_op_brev8; break;
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}
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break;