target/riscv: Report QEMU CPU archid as 42
When a non-vendor CPU is used, report the archid as 42 which has been allocated for QEMU in the riscv isa manual [1]. This can help software check if it is running in QEMU. [1] https://github.com/riscv/riscv-isa-manual/blob/main/marchid.md Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Message-ID: <20260625-marchid-v2-1-3821c351028b@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Charlie Jenkins committed
Jun 25, 2026 at 22:12 UTC
d6c782fdb9f0c98ccf8e54d70165420e58e3c767
1 file changed
+11
target/riscv/cpu.c
+11
@@ -47,6 +47,13 @@
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static const char riscv_single_letter_exts[] = "IEMAFDQCBPVH";
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const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
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RVC, RVS, RVU, RVH, RVG, RVB, 0};
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+#define RISCV_CPU_MVENDORID 0
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+#define RISCV_CPU_MIMPID 0
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+/*
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+ * marchid allocated for qemu:
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+ * https://github.com/riscv/riscv-isa-manual/blob/main/marchid.md
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+ */
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+#define RISCV_CPU_MARCHID 42
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/*
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* From vector_helper.c
@@ -1204,6 +1211,10 @@ static void riscv_cpu_init(Object *obj)
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mcc->def->profile->enabled = true;
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}
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+ cpu->cfg.mvendorid = RISCV_CPU_MVENDORID;
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+ cpu->cfg.marchid = RISCV_CPU_MARCHID;
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+ cpu->cfg.mimpid = RISCV_CPU_MIMPID;
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+
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env->misa_ext_mask = env->misa_ext = mcc->def->misa_ext;
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riscv_cpu_cfg_merge(&cpu->cfg, &mcc->def->cfg);
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