target/hexagon: handle misaligned load/store cause codes in cpu_loop
Add a linux-user cpu_loop handler for HEX_CAUSE_MISALIGNED_LOAD and HEX_CAUSE_MISALIGNED_STORE, raising SIGBUS for consistency with hexswi.c's sysemu handling, even though linux-user's own alignment check in accel/tcg/user-exec.c currently raises SIGBUS before Hexagon's cause-code machinery is reached. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Reviewed-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Brian Cain committed
Jul 13, 2026 at 18:09 UTC
d7a6df755b97c959925cad5439e2c688d08b268f
1 file changed
+5
linux-user/hexagon/cpu_loop.c
+5
@@ -76,6 +76,11 @@ void cpu_loop(CPUHexagonState *env)
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force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC,
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env->gpr[HEX_REG_PC]);
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break;
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+ case HEX_CAUSE_MISALIGNED_LOAD:
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+ case HEX_CAUSE_MISALIGNED_STORE:
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+ force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN,
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+ env->gpr[HEX_REG_PC]);
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+ break;
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default:
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EXCP_DUMP(env, "\nqemu: unhandled CPU precise exception "
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"cause code 0x%x - aborting\n",