target/ppc: Reorder PPC2 flags
Consolidation of different variations of Power ISA 2.07 flags into the PPC2_ISA207 flag has left gaps in the flag encoding. This patch reorders them, restoring the expected incremental order without any gaps, freeing up bits for future use. Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Tested-by: Aniket Sahu <asahu1x@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-36-rathc@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Chinmay Rath committed
Aug 27, 2026 at 18:59 UTC
d835c1b4ffd365212d32ddd36a11b8cfa181ca56
1 file changed
+10
-10
target/ppc/cpu.h
+10
-10
@@ -2578,25 +2578,25 @@ enum {
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/* ISA 2.06B floating point test instructions */
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PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
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/* Double precision floating point conversion for signed integer 64 */
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- PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
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+ PPC2_FP_CVT_S64 = 0x0000000000001000ULL,
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/* Transactional Memory (ISA 2.07, Book II) */
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- PPC2_TM = 0x0000000000020000ULL,
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+ PPC2_TM = 0x0000000000002000ULL,
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/* Server PM instructgions (ISA 2.06, Book III) */
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- PPC2_PM_ISA206 = 0x0000000000040000ULL,
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+ PPC2_PM_ISA206 = 0x0000000000004000ULL,
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/* POWER ISA 3.0 */
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- PPC2_ISA300 = 0x0000000000080000ULL,
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+ PPC2_ISA300 = 0x0000000000008000ULL,
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/* POWER ISA 3.1 */
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- PPC2_ISA310 = 0x0000000000100000ULL,
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+ PPC2_ISA310 = 0x0000000000010000ULL,
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/* lwsync instruction */
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- PPC2_MEM_LWSYNC = 0x0000000000200000ULL,
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+ PPC2_MEM_LWSYNC = 0x0000000000020000ULL,
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/* ISA 2.06 BCD assist instructions */
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- PPC2_BCDA_ISA206 = 0x0000000000400000ULL,
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+ PPC2_BCDA_ISA206 = 0x0000000000040000ULL,
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/* PPE42 instructions */
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- PPC2_PPE42 = 0x0000000000800000ULL,
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+ PPC2_PPE42 = 0x0000000000080000ULL,
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/* PPE42X instructions */
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- PPC2_PPE42X = 0x0000000001000000ULL,
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+ PPC2_PPE42X = 0x0000000000100000ULL,
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/* PPE42XM instructions */
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- PPC2_PPE42XM = 0x0000000002000000ULL,
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+ PPC2_PPE42XM = 0x0000000000200000ULL,
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#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
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PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \