@samitouri / QOSamiQemu / commits / d85a4ec06a

target/riscv/cpu_helper.c: allow LOAD_ADDR_MIS promotion to AMO fault

promote_load_fault() is missing the promotion of misaligned AMO load addresses, i.e. RISCV_EXCP_LOAD_ADDR_MIS should be promoted to RISCV_EXCP_STORE_AMO_ADDR_MIS when RISCV_UW2_ALWAYS_STORE_AMO (i.e. always_storeamo is true). All other load AMO faults are already being covered. Cc: qemu-stable@nongnu.org Fixes: 98f21c30f5 ("target/riscv: AMO operations always raise store/AMO fault") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3503 Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com> Message-ID: <20260522181353.429782-1-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Daniel Henrique Barboza committed May 22, 2026 at 15:13 UTC d85a4ec06a65ccdd5c7d0f00b3e6695fc14a547a

1 file changed +3

target/riscv/cpu_helper.c

@@ -2210,6 +2210,9 @@ static target_ulong promote_load_fault(target_ulong orig_cause)

2210

2211 case RISCV_EXCP_LOAD_PAGE_FAULT:

2212 return RISCV_EXCP_STORE_PAGE_FAULT;

2213 +

2214 + case RISCV_EXCP_LOAD_ADDR_MIS:

2215 + return RISCV_EXCP_STORE_AMO_ADDR_MIS;

2216 }

2217

2218 /* if no promotion, return original cause */