hw/watchdog: add k230 watchdog initial support
Add programmable Watchdog Timer (WDT) peripheral for K230 machine. Signed-off-by: Mig Yang <temashking@foxmail.com> Signed-off-by: Chao Liu <chao.liu.zevorn@gmail.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Message-ID: <805a04d9467556ee6a5f4742c9eb4bbb6fc7898c.1781246408.git.chao.liu@processmission.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Chao Liu committed
Jun 12, 2026 at 15:04 UTC
dace398674df8af11df13f2554e8566e9de3f8c7
9 files changed
+456
MAINTAINERS
+2
@@ -1791,7 +1791,9 @@ M: Chao Liu <chao.liu.zevorn@gmail.com>
1791
L: qemu-riscv@nongnu.org
1792
S: Maintained
1793
F: hw/riscv/k230.c
1794
+F: hw/watchdog/k230_wdt.c
1795
F: include/hw/riscv/k230.h
1796
+F: include/hw/watchdog/k230_wdt.h
1797
1798
RX Machines
1799
-----------
hw/riscv/Kconfig
+1
@@ -148,3 +148,4 @@ config K230
148
select RISCV_IMSIC
149
select SERIAL_MM
150
select UNIMP
151
+ select K230_WDT
hw/riscv/k230.c
+18
@@ -108,6 +108,9 @@ static void k230_soc_init(Object *obj)
108
RISCVHartArrayState *cpu0 = &s->c908_cpu;
109
110
object_initialize_child(obj, "c908-cpu", cpu0, TYPE_RISCV_HART_ARRAY);
111
+ object_initialize_child(obj, "k230-wdt0", &s->wdt[0], TYPE_K230_WDT);
112
+ object_initialize_child(obj, "k230-wdt1", &s->wdt[1], TYPE_K230_WDT);
113
+
114
qdev_prop_set_uint32(DEVICE(cpu0), "hartid-base", 0);
115
qdev_prop_set_string(DEVICE(cpu0), "cpu-type", TYPE_RISCV_CPU_THEAD_C908);
116
qdev_prop_set_uint64(DEVICE(cpu0), "resetvec",
@@ -188,6 +191,21 @@ static void k230_soc_realize(DeviceState *dev, Error **errp)
191
k230_create_uart(sys_mem, DEVICE(s->c908_plic), i);
192
}
193
194
+ /* Watchdog */
195
+ for (int i = 0; i < 2; i++) {
196
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
197
+ return;
198
+ }
199
+ }
200
+
201
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[0]), 0, memmap[K230_DEV_WDT0].base);
202
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[0]), 0,
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+ qdev_get_gpio_in(DEVICE(s->c908_plic), K230_WDT0_IRQ));
204
+
205
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[1]), 0, memmap[K230_DEV_WDT1].base);
206
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[1]), 0,
207
+ qdev_get_gpio_in(DEVICE(s->c908_plic), K230_WDT1_IRQ));
208
+
209
/* unimplemented devices */
210
create_unimplemented_device("kpu.l2-cache",
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memmap[K230_DEV_KPU_L2_CACHE].base,
hw/watchdog/Kconfig
+4
@@ -18,6 +18,10 @@ config WDT_DIAG288
18
config WDT_IMX2
19
bool
20
21
+config K230_WDT
22
+ bool
23
+ select PTIMER
24
+
25
config WDT_SBSA
26
bool
27
hw/watchdog/k230_wdt.c
new
+296
@@ -0,0 +1,296 @@
1
+/*
2
+ * K230 Watchdog Compatible with kendryte K230 SDK
3
+ *
4
+ * Copyright (c) 2025 Mig Yang <temashking@foxmail.com>
5
+ * Copyright (c) 2025 Chao Liu <chao.liu.zevorn@gmail.com>
6
+ *
7
+ * SPDX-License-Identifier: GPL-2.0-or-later
8
+ *
9
+ * Provides a board compatible with the kendryte K230 SDK
10
+ *
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+ * K230 Technical Reference Manual V0.3.1 (2024-11-18):
12
+ * https://github.com/revyos/external-docs/blob/master/K230/en-us/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf
13
+ *
14
+ * For more information, see <https://www.kendryte.com/en/proDetail/230>
15
+ */
16
+#include "qemu/osdep.h"
17
+#include "qemu/bitops.h"
18
+#include "qemu/module.h"
19
+#include "system/watchdog.h"
20
+#include "migration/vmstate.h"
21
+#include "hw/core/qdev-properties.h"
22
+#include "hw/watchdog/k230_wdt.h"
23
+#include "trace.h"
24
+
25
+static void k230_wdt_timeout(void *opaque)
26
+{
27
+ K230WdtState *s = K230_WDT(opaque);
28
+
29
+ trace_k230_wdt_timeout();
30
+
31
+ /* Set interrupt status if in interrupt mode */
32
+ if (s->cr & K230_WDT_CR_RMOD) {
33
+ s->stat |= K230_WDT_STAT_INT;
34
+ s->interrupt_pending = true;
35
+ qemu_set_irq(s->irq, 1);
36
+ trace_k230_wdt_interrupt();
37
+ } else {
38
+ /* Direct reset mode */
39
+ trace_k230_wdt_reset();
40
+ watchdog_perform_action();
41
+ }
42
+
43
+ /* Restart counter */
44
+ s->current_count = s->timeout_value;
45
+ ptimer_set_count(s->timer, s->current_count);
46
+ ptimer_run(s->timer, 1);
47
+}
48
+
49
+static void k230_wdt_reset(DeviceState *dev)
50
+{
51
+ K230WdtState *s = K230_WDT(dev);
52
+
53
+ trace_k230_wdt_reset_device();
54
+
55
+ ptimer_transaction_begin(s->timer);
56
+ ptimer_stop(s->timer);
57
+ ptimer_transaction_commit(s->timer);
58
+
59
+ /* Reset registers to default values */
60
+ s->cr = 0;
61
+ s->torr = 0;
62
+ s->ccvr = 0xFFFFFFFF;
63
+ s->stat = 0;
64
+ s->prot_level = 0x2;
65
+
66
+ s->interrupt_pending = false;
67
+ s->enabled = false;
68
+ s->timeout_value = 0;
69
+ s->current_count = 0xFFFFFFFF;
70
+}
71
+
72
+static uint64_t k230_wdt_read(void *opaque, hwaddr addr, unsigned int size)
73
+{
74
+ K230WdtState *s = K230_WDT(opaque);
75
+ uint32_t value = 0;
76
+
77
+ switch (addr) {
78
+ case K230_WDT_CR:
79
+ value = s->cr;
80
+ break;
81
+ case K230_WDT_TORR:
82
+ value = s->torr;
83
+ break;
84
+ case K230_WDT_CCVR:
85
+ if (s->enabled) {
86
+ value = ptimer_get_count(s->timer);
87
+ } else {
88
+ value = s->current_count;
89
+ }
90
+ break;
91
+ case K230_WDT_STAT:
92
+ value = s->stat;
93
+ break;
94
+ case K230_WDT_PROT_LEVEL:
95
+ value = s->prot_level;
96
+ break;
97
+ case K230_WDT_COMP_PARAM_5:
98
+ value = 0; /* Upper limit of Timeout Period parameters */
99
+ break;
100
+ case K230_WDT_COMP_PARAM_4:
101
+ value = 0; /* Upper limit of Initial Timeout Period parameters */
102
+ break;
103
+ case K230_WDT_COMP_PARAM_3:
104
+ value = 0; /* Derived from WDT_TOP_RST parameter */
105
+ break;
106
+ case K230_WDT_COMP_PARAM_2:
107
+ value = 0xFFFFFFFF; /* Derived from WDT_RST_CNT parameter */
108
+ break;
109
+ case K230_WDT_COMP_PARAM_1:
110
+ /* Component parameters */
111
+ value = (32 << K230_WDT_CNT_WIDTH_SHIFT) | /* 32-bit counter */
112
+ (0 << K230_WDT_DFLT_TOP_INIT_SHIFT) |
113
+ (0 << K230_WDT_DFLT_TOP_SHIFT) |
114
+ (K230_WDT_RPL_16_CYCLES << K230_WDT_DFLT_RPL_SHIFT) |
115
+ (2 << K230_WDT_APB_DATA_WIDTH_SHIFT) | /* 32-bit APB */
116
+ K230_WDT_USE_FIX_TOP; /* Use fixed timeout values */
117
+ break;
118
+ case K230_WDT_COMP_VERSION:
119
+ value = K230_WDT_COMP_VERSION_VAL;
120
+ break;
121
+ case K230_WDT_COMP_TYPE:
122
+ value = K230_WDT_COMP_TYPE_VAL;
123
+ break;
124
+ default:
125
+ /* Other registers return 0 */
126
+ break;
127
+ }
128
+
129
+ trace_k230_wdt_read(addr, value);
130
+ return value;
131
+}
132
+
133
+static void k230_wdt_update_timer(K230WdtState *s)
134
+{
135
+ ptimer_transaction_begin(s->timer);
136
+
137
+ if (s->enabled && s->timeout_value > 0) {
138
+ ptimer_set_count(s->timer, s->current_count);
139
+ ptimer_run(s->timer, 1);
140
+ } else {
141
+ ptimer_stop(s->timer);
142
+ }
143
+
144
+ ptimer_transaction_commit(s->timer);
145
+}
146
+
147
+static uint32_t k230_wdt_calculate_timeout(uint32_t top_value)
148
+{
149
+ /* Calculate timeout based on TOP value */
150
+ /* For fixed timeout mode: 2^(16 + top_value) */
151
+ if (top_value <= 15) {
152
+ return 1 << (16 + top_value);
153
+ }
154
+ return 1 << 31; /* Maximum value for 32-bit counter */
155
+}
156
+
157
+static void k230_wdt_write(void *opaque, hwaddr addr,
158
+ uint64_t value, unsigned int size)
159
+{
160
+ K230WdtState *s = K230_WDT(opaque);
161
+
162
+ trace_k230_wdt_write(addr, value);
163
+
164
+ switch (addr) {
165
+ case K230_WDT_CR:
166
+ s->cr = value & (K230_WDT_CR_RPL_MASK << K230_WDT_CR_RPL_SHIFT |
167
+ K230_WDT_CR_RMOD | K230_WDT_CR_WDT_EN);
168
+
169
+ /* Update enabled state */
170
+ s->enabled = (s->cr & K230_WDT_CR_WDT_EN) != 0;
171
+
172
+ /* Update timer */
173
+ k230_wdt_update_timer(s);
174
+ break;
175
+
176
+ case K230_WDT_TORR:
177
+ s->torr = value & K230_WDT_TORR_TOP_MASK;
178
+
179
+ /* Calculate new timeout value */
180
+ s->timeout_value = k230_wdt_calculate_timeout(s->torr);
181
+ s->current_count = s->timeout_value;
182
+
183
+ /* Update timer if enabled */
184
+ if (s->enabled) {
185
+ k230_wdt_update_timer(s);
186
+ }
187
+ break;
188
+
189
+ case K230_WDT_CRR:
190
+ /* Restart counter with magic value 0x76 */
191
+ if ((value & 0xFF) == K230_WDT_CRR_RESTART) {
192
+ trace_k230_wdt_restart();
193
+ s->current_count = s->timeout_value;
194
+
195
+ /* Clear interrupt if pending */
196
+ if (s->interrupt_pending) {
197
+ s->stat &= ~K230_WDT_STAT_INT;
198
+ s->interrupt_pending = false;
199
+ qemu_set_irq(s->irq, 0);
200
+ }
201
+
202
+ /* Update timer */
203
+ k230_wdt_update_timer(s);
204
+ }
205
+ break;
206
+
207
+ case K230_WDT_EOI:
208
+ /* Clear interrupt */
209
+ s->stat &= ~K230_WDT_STAT_INT;
210
+ s->interrupt_pending = false;
211
+ qemu_set_irq(s->irq, 0);
212
+ break;
213
+
214
+ case K230_WDT_PROT_LEVEL:
215
+ s->prot_level = value & 0x7;
216
+ break;
217
+
218
+ default:
219
+ /* Read-only registers, ignore writes */
220
+ break;
221
+ }
222
+}
223
+
224
+static const MemoryRegionOps k230_wdt_ops = {
225
+ .read = k230_wdt_read,
226
+ .write = k230_wdt_write,
227
+ .endianness = DEVICE_LITTLE_ENDIAN,
228
+ .impl = {
229
+ .min_access_size = 4,
230
+ .max_access_size = 4,
231
+ .unaligned = false,
232
+ },
233
+};
234
+
235
+static const VMStateDescription vmstate_k230_wdt = {
236
+ .name = "k230.wdt",
237
+ .fields = (const VMStateField[]) {
238
+ VMSTATE_PTIMER(timer, K230WdtState),
239
+ VMSTATE_UINT32(cr, K230WdtState),
240
+ VMSTATE_UINT32(torr, K230WdtState),
241
+ VMSTATE_UINT32(ccvr, K230WdtState),
242
+ VMSTATE_UINT32(stat, K230WdtState),
243
+ VMSTATE_UINT32(prot_level, K230WdtState),
244
+ VMSTATE_BOOL(interrupt_pending, K230WdtState),
245
+ VMSTATE_BOOL(enabled, K230WdtState),
246
+ VMSTATE_UINT32(timeout_value, K230WdtState),
247
+ VMSTATE_UINT32(current_count, K230WdtState),
248
+ VMSTATE_END_OF_LIST()
249
+ }
250
+};
251
+
252
+static void k230_wdt_realize(DeviceState *dev, Error **errp)
253
+{
254
+ K230WdtState *s = K230_WDT(dev);
255
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
256
+
257
+ memory_region_init_io(&s->mmio, OBJECT(dev),
258
+ &k230_wdt_ops, s,
259
+ TYPE_K230_WDT,
260
+ K230_WDT_MMIO_SIZE);
261
+ sysbus_init_mmio(sbd, &s->mmio);
262
+ sysbus_init_irq(sbd, &s->irq);
263
+
264
+ s->timer = ptimer_init(k230_wdt_timeout, s,
265
+ PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |
266
+ PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
267
+ PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
268
+
269
+ ptimer_transaction_begin(s->timer);
270
+ ptimer_set_freq(s->timer, K230_WDT_DEFAULT_FREQ);
271
+ ptimer_transaction_commit(s->timer);
272
+}
273
+
274
+static void k230_wdt_class_init(ObjectClass *klass, const void *data)
275
+{
276
+ DeviceClass *dc = DEVICE_CLASS(klass);
277
+
278
+ dc->realize = k230_wdt_realize;
279
+ device_class_set_legacy_reset(dc, k230_wdt_reset);
280
+ dc->vmsd = &vmstate_k230_wdt;
281
+ dc->desc = "K230 watchdog timer";
282
+ set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories);
283
+}
284
+
285
+static const TypeInfo k230_wdt_info = {
286
+ .name = TYPE_K230_WDT,
287
+ .parent = TYPE_SYS_BUS_DEVICE,
288
+ .instance_size = sizeof(K230WdtState),
289
+ .class_init = k230_wdt_class_init,
290
+};
291
+
292
+static void k230_wdt_register_type(void)
293
+{
294
+ type_register_static(&k230_wdt_info);
295
+}
296
+type_init(k230_wdt_register_type)
hw/watchdog/meson.build
+1
@@ -6,5 +6,6 @@ system_ss.add(when: 'CONFIG_WDT_IB700', if_true: files('wdt_ib700.c'))
6
system_ss.add(when: 'CONFIG_WDT_DIAG288', if_true: files('wdt_diag288.c'))
7
system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('wdt_aspeed.c'))
8
system_ss.add(when: 'CONFIG_WDT_IMX2', if_true: files('wdt_imx2.c'))
9
+system_ss.add(when: 'CONFIG_K230_WDT', if_true: files('k230_wdt.c'))
10
system_ss.add(when: 'CONFIG_WDT_SBSA', if_true: files('sbsa_gwdt.c'))
11
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_watchdog.c'))
hw/watchdog/trace-events
+9
@@ -33,3 +33,12 @@ spapr_watchdog_expired(uint64_t num, unsigned action) "num=%" PRIu64 " action=%u
33
# watchdog.c
34
watchdog_perform_action(unsigned int action) "action=%u"
35
watchdog_set_action(unsigned int action) "action=%u"
36
+
37
+# k230_wdt.c
38
+k230_wdt_read(uint64_t addr, uint32_t data) "K230 WDT read: [0x%" PRIx64 "] -> 0x%" PRIx32
39
+k230_wdt_write(uint64_t addr, uint64_t data) "K230 WDT write: [0x%" PRIx64 "] <- 0x%" PRIx64
40
+k230_wdt_timeout(void) "K230 WDT timeout"
41
+k230_wdt_interrupt(void) "K230 WDT interrupt"
42
+k230_wdt_reset(void) "K230 WDT system reset"
43
+k230_wdt_restart(void) "K230 WDT restart"
44
+k230_wdt_reset_device(void) "K230 WDT device reset"
include/hw/riscv/k230.h
+4
@@ -17,6 +17,7 @@
17
18
#include "hw/core/boards.h"
19
#include "hw/riscv/riscv_hart.h"
20
+#include "hw/watchdog/k230_wdt.h"
21
22
#define C908_CPU_HARTID (0)
23
@@ -31,6 +32,7 @@ typedef struct K230SoCState {
32
/*< public >*/
33
RISCVHartArrayState c908_cpu; /* Small core */
34
35
+ K230WdtState wdt[2];
36
MemoryRegion sram;
37
MemoryRegion bootrom;
38
@@ -125,6 +127,8 @@ enum {
127
K230_UART2_IRQ = 18,
128
K230_UART3_IRQ = 19,
129
K230_UART4_IRQ = 20,
130
+ K230_WDT0_IRQ = 107,
131
+ K230_WDT1_IRQ = 108,
132
};
133
134
#define K230_UART_COUNT 5
include/hw/watchdog/k230_wdt.h
new
+121
@@ -0,0 +1,121 @@
1
+/*
2
+ * K230 Watchdog Timer
3
+ *
4
+ * K230 Technical Reference Manual V0.3.1 (2024-11-18):
5
+ * https://github.com/revyos/external-docs/blob/master/K230/en-us/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf
6
+ *
7
+ * Copyright (c) 2025 Mig Yang <temashking@foxmail.com>
8
+ * Copyright (c) 2025 Chao Liu <chao.liu.zevorn@gmail.com>
9
+ *
10
+ * SPDX-License-Identifier: GPL-2.0-or-later
11
+ */
12
+
13
+#ifndef K230_WDT_H
14
+#define K230_WDT_H
15
+
16
+#include "qemu/bitops.h"
17
+#include "hw/core/sysbus.h"
18
+#include "hw/core/irq.h"
19
+#include "hw/core/ptimer.h"
20
+#include "qom/object.h"
21
+
22
+#define TYPE_K230_WDT "riscv.k230.wdt"
23
+OBJECT_DECLARE_SIMPLE_TYPE(K230WdtState, K230_WDT)
24
+
25
+#define K230_WDT_DEFAULT_FREQ (32768)
26
+
27
+/* K230 Watchdog Register Map */
28
+enum K230WdtRegisters {
29
+ K230_WDT_CR = 0x00, /* Control Register */
30
+ K230_WDT_TORR = 0x04, /* Timeout Range Register */
31
+ K230_WDT_CCVR = 0x08, /* Current Counter Value Register */
32
+ K230_WDT_CRR = 0x0c, /* Counter Restart Register */
33
+ K230_WDT_STAT = 0x10, /* Interrupt Status Register */
34
+ K230_WDT_EOI = 0x14, /* Interrupt Clear Register */
35
+ K230_WDT_PROT_LEVEL = 0x1c, /* Protection Level Register */
36
+ K230_WDT_COMP_PARAM_5 = 0xe4, /* Component Parameters Register 5 */
37
+ K230_WDT_COMP_PARAM_4 = 0xe8, /* Component Parameters Register 4 */
38
+ K230_WDT_COMP_PARAM_3 = 0xec, /* Component Parameters Register 3 */
39
+ K230_WDT_COMP_PARAM_2 = 0xf0, /* Component Parameters Register 2 */
40
+ K230_WDT_COMP_PARAM_1 = 0xf4, /* Component Parameters Register 1 */
41
+ K230_WDT_COMP_VERSION = 0xf8, /* Component Version Register */
42
+ K230_WDT_COMP_TYPE = 0xfc, /* Component Type Register */
43
+};
44
+
45
+#define K230_WDT_MMIO_SIZE 0x100
46
+
47
+/* Control Register (WDT_CR) definitions */
48
+#define K230_WDT_CR_RPL_MASK 0x7 /* Reset Pulse Length */
49
+#define K230_WDT_CR_RPL_SHIFT 2
50
+#define K230_WDT_CR_RMOD BIT(1) /* Response Mode */
51
+#define K230_WDT_CR_WDT_EN BIT(0) /* Watchdog Enable */
52
+
53
+/* Reset Pulse Length values */
54
+#define K230_WDT_RPL_2_CYCLES 0x0
55
+#define K230_WDT_RPL_4_CYCLES 0x1
56
+#define K230_WDT_RPL_8_CYCLES 0x2
57
+#define K230_WDT_RPL_16_CYCLES 0x3
58
+#define K230_WDT_RPL_32_CYCLES 0x4
59
+#define K230_WDT_RPL_64_CYCLES 0x5
60
+#define K230_WDT_RPL_128_CYCLES 0x6
61
+#define K230_WDT_RPL_256_CYCLES 0x7
62
+
63
+/* Timeout Range Register (WDT_TORR) definitions */
64
+#define K230_WDT_TORR_TOP_MASK 0xf /* Timeout Period */
65
+
66
+/* Interrupt Status Register (WDT_STAT) definitions */
67
+#define K230_WDT_STAT_INT BIT(0) /* Interrupt Status */
68
+
69
+/* Counter Restart Register (WDT_CRR) magic value */
70
+#define K230_WDT_CRR_RESTART 0x76 /* Restart command */
71
+
72
+/* Component Parameters Register 1 (WDT_COMP_PARAM_1) definitions */
73
+#define K230_WDT_CNT_WIDTH_MASK 0x1f000000 /* Counter Width */
74
+#define K230_WDT_CNT_WIDTH_SHIFT 24
75
+#define K230_WDT_DFLT_TOP_INIT_MASK 0xf00000 /* Default Initial Timeout */
76
+#define K230_WDT_DFLT_TOP_INIT_SHIFT 20
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+#define K230_WDT_DFLT_TOP_MASK 0xf0000 /* Default Timeout */
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+#define K230_WDT_DFLT_TOP_SHIFT 16
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+#define K230_WDT_DFLT_RPL_MASK 0x7 /* Default Reset Pulse Length */
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+#define K230_WDT_DFLT_RPL_SHIFT 10
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+#define K230_WDT_APB_DATA_WIDTH_MASK 0x3 /* APB Data Width */
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+#define K230_WDT_APB_DATA_WIDTH_SHIFT 8
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+#define K230_WDT_USE_FIX_TOP BIT(6) /* Use Fixed Timeout Values */
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+#define K230_WDT_HC_TOP BIT(5) /* Hard-coded Timeout */
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+#define K230_WDT_HC_RPL BIT(4) /* Hard-coded Reset Pulse Length */
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+#define K230_WDT_HC_RMOD BIT(3) /* Hard-coded Response Mode */
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+#define K230_WDT_DUAL_TOP BIT(2) /* Dual Timeout Period */
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+#define K230_WDT_DFLT_RMOD BIT(1) /* Default Response Mode */
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+#define K230_WDT_ALWAYS_EN BIT(0) /* Always Enabled */
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+
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+/* Component Type Register value */
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+#define K230_WDT_COMP_TYPE_VAL 0x44570120
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+
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+/* Component Version Register value */
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+#define K230_WDT_COMP_VERSION_VAL 0x3131302a /* "110*" */
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+
97
+struct K230WdtState {
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+ /* <private> */
99
+ SysBusDevice parent_obj;
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+
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+ /*< public >*/
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+ MemoryRegion mmio;
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+ qemu_irq irq;
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+
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+ struct ptimer_state *timer;
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+
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+ /* Register state */
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+ uint32_t cr; /* Control Register */
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+ uint32_t torr; /* Timeout Range Register */
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+ uint32_t ccvr; /* Current Counter Value Register */
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+ uint32_t stat; /* Interrupt Status Register */
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+ uint32_t prot_level; /* Protection Level Register */
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+
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+ /* Internal state */
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+ bool interrupt_pending;
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+ bool enabled;
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+ uint32_t timeout_value;
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+ uint32_t current_count;
119
+};
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+
121
+#endif /* K230_WDT_H */