@samitouri / QOSamiQemu / commits / db19ef221f

hw/i3c: rename DW-I3C queue capacity fields from _bytes to _words

The cmd/resp, tx/rx, and IBI queue capacity values are passed straight to fifo32_create(), which interprets its capacity argument as a 32-bit word count. The fields and device properties were therefore misnamed: setting e.g. tx-rx-queue-capacity-bytes=N sized the backing FIFO to N words, not N bytes. Rename the three struct fields and matching device-property strings: cmd_resp_queue_capacity_bytes -> cmd_resp_queue_capacity_words tx_rx_queue_capacity_bytes -> tx_rx_queue_capacity_words ibi_queue_capacity_bytes -> ibi_queue_capacity_words Defaults are unchanged (0x10 / 0x40 / 0x10) -- they were being interpreted as word counts by fifo32_create() all along, just under a misleading label. No behavioral change. Signed-off-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20260604142207.2118098-3-jithu.joseph@oss.qualcomm.com Signed-off-by: Cédric Le Goater <clg@redhat.com>

Jithu Joseph committed Jun 4, 2026 at 07:22 UTC db19ef221f241ae35be0887ec05b36b69e4a647c

2 files changed +19 -19

hw/i3c/dw-i3c.c

+16 -16

@@ -948,9 +948,9 @@ static void dw_i3c_reset(DeviceState *dev)

948 ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH,

949 s->cfg.dev_char_table_depth);

950 ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC,

951 - s->cfg.cmd_resp_queue_capacity_bytes);

951 + s->cfg.cmd_resp_queue_capacity_words);

952 ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC,

953 - s->cfg.tx_rx_queue_capacity_bytes);

953 + s->cfg.tx_rx_queue_capacity_words);

954

955 dw_i3c_cmd_queue_reset(s);

956 dw_i3c_resp_queue_reset(s);

@@ -1798,9 +1798,9 @@ static void dw_i3c_reset_enter(Object *obj, ResetType type)

1798 ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH,

1799 s->cfg.dev_char_table_depth);

1800 ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC,

1801 - s->cfg.cmd_resp_queue_capacity_bytes);

1801 + s->cfg.cmd_resp_queue_capacity_words);

1802 ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC,

1803 - s->cfg.tx_rx_queue_capacity_bytes);

1803 + s->cfg.tx_rx_queue_capacity_words);

1804 }

1805

1806 static void dw_i3c_realize(DeviceState *dev, Error **errp)

@@ -1814,14 +1814,14 @@ static void dw_i3c_realize(DeviceState *dev, Error **errp)

1814 DW_I3C_NR_REGS << 2);

1815 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr);

1816

1817 - fifo32_create(&s->cmd_queue, s->cfg.cmd_resp_queue_capacity_bytes);

1818 - fifo32_create(&s->resp_queue, s->cfg.cmd_resp_queue_capacity_bytes);

1819 - fifo32_create(&s->tx_queue, s->cfg.tx_rx_queue_capacity_bytes);

1820 - fifo32_create(&s->rx_queue, s->cfg.tx_rx_queue_capacity_bytes);

1821 - fifo32_create(&s->ibi_queue, s->cfg.ibi_queue_capacity_bytes);

1817 + fifo32_create(&s->cmd_queue, s->cfg.cmd_resp_queue_capacity_words);

1818 + fifo32_create(&s->resp_queue, s->cfg.cmd_resp_queue_capacity_words);

1819 + fifo32_create(&s->tx_queue, s->cfg.tx_rx_queue_capacity_words);

1820 + fifo32_create(&s->rx_queue, s->cfg.tx_rx_queue_capacity_words);

1821 + fifo32_create(&s->ibi_queue, s->cfg.ibi_queue_capacity_words);

1822 /* Arbitrarily large enough to not be an issue. */

1823 fifo8_create(&s->ibi_data.ibi_intermediate_queue,

1824 - s->cfg.ibi_queue_capacity_bytes * 8);

1824 + s->cfg.ibi_queue_capacity_words * 8);

1825

1826 s->bus = i3c_init_bus(DEVICE(s), name);

1827 I3CBusClass *bc = I3C_BUS_GET_CLASS(s->bus);

@@ -1832,12 +1832,12 @@ static void dw_i3c_realize(DeviceState *dev, Error **errp)

1832

1833 static const Property dw_i3c_properties[] = {

1834 DEFINE_PROP_UINT8("device-id", DWI3C, cfg.id, 0),

1835 - DEFINE_PROP_UINT8("command-response-queue-capacity-bytes", DWI3C,

1836 - cfg.cmd_resp_queue_capacity_bytes, 0x10),

1837 - DEFINE_PROP_UINT16("tx-rx-queue-capacity-bytes", DWI3C,

1838 - cfg.tx_rx_queue_capacity_bytes, 0x40),

1839 - DEFINE_PROP_UINT8("ibi-queue-capacity-bytes", DWI3C,

1840 - cfg.ibi_queue_capacity_bytes, 0x10),

1835 + DEFINE_PROP_UINT8("command-response-queue-capacity-words", DWI3C,

1836 + cfg.cmd_resp_queue_capacity_words, 0x10),

1837 + DEFINE_PROP_UINT16("tx-rx-queue-capacity-words", DWI3C,

1838 + cfg.tx_rx_queue_capacity_words, 0x40),

1839 + DEFINE_PROP_UINT8("ibi-queue-capacity-words", DWI3C,

1840 + cfg.ibi_queue_capacity_words, 0x10),

1841 DEFINE_PROP_UINT8("num-addressable-devices", DWI3C,

1842 cfg.num_addressable_devices, 8),

1843 DEFINE_PROP_UINT16("dev-addr-table-pointer", DWI3C,

include/hw/i3c/dw-i3c.h

+3 -3

@@ -181,9 +181,9 @@ struct DWI3C {

181

182 struct {

183 uint8_t id;

184 - uint8_t cmd_resp_queue_capacity_bytes;

185 - uint16_t tx_rx_queue_capacity_bytes;

186 - uint8_t ibi_queue_capacity_bytes;

184 + uint8_t cmd_resp_queue_capacity_words;

185 + uint16_t tx_rx_queue_capacity_words;

186 + uint8_t ibi_queue_capacity_words;

187 uint8_t num_addressable_devices;

188 uint16_t dev_addr_table_pointer;

189 uint16_t dev_addr_table_depth;