target/arm: Implement DBGDEVID* registers in max AArch32 CPU
32-bit ARM max CPU is a 'Cortex-A57 advertising none of the AArch64 features'. Keep it as close as possible as the A57, by implementing the debug ID registers, following the changes in aarch64_a57_initfn added by commits 48eb3ae64b3 ("target-arm: Adjust debug ID registers per-CPU") and 09754ca867f ("target/arm: Implement AArch32 DBGDEVID, DBGDEVID1, DBGDEVID2"). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20260526203722.79463-12-philmd@linaro.org>
Philippe Mathieu-Daudé committed
May 13, 2026 at 11:26 UTC
db8b42184c5564c72c066e0674b116905ce58ede
1 file changed
+3
target/arm/tcg/cpu32.c
+3
@@ -755,6 +755,9 @@ static void arm_max_initfn(Object *obj)
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SET_IDREG(isar, ID_ISAR4, 0x00011142);
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SET_IDREG(isar, ID_ISAR5, 0x00011121);
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SET_IDREG(isar, ID_ISAR6, 0);
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+ cpu->isar.dbgdidr = 0x3516d000;
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+ cpu->isar.dbgdevid = 0x01110f13;
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+ cpu->isar.dbgdevid1 = 0x2;
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cpu->isar.reset_pmcr_el0 = 0x41013000;
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SET_IDREG(isar, CLIDR, 0x0a200023);
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/* 32KB L1 dcache */