target/riscv: Fix size of [m|s|vs]iselect fields
[m|s|vs]iselect are defined in version 20250508 of the privileged specification to be XLEN in size, however QEMU only ever uses at most 16 bits of these fields, so fix them to 16. Update relevant function arguments. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260520125406.28693-15-anjo@rev.ng> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anton Johansson committed
May 20, 2026 at 14:53 UTC
db9383ce37d251278c5612aed24a45b2b349be4d
3 files changed
+23
-23
target/riscv/cpu.h
+4
-4
@@ -344,8 +344,8 @@ struct CPUArchState {
344
uint8_t siprio[64];
345
346
/* AIA CSRs */
347
- target_ulong miselect;
348
- target_ulong siselect;
347
+ uint16_t miselect;
348
+ uint16_t siselect;
349
uint64_t mvien;
350
uint64_t mvip;
351
@@ -391,7 +391,7 @@ struct CPUArchState {
391
uint64_t vsatp;
392
393
/* AIA VS-mode CSRs */
394
- target_ulong vsiselect;
394
+ uint16_t vsiselect;
395
396
uint64_t mtval2;
397
uint64_t mtinst;
@@ -794,7 +794,7 @@ static inline RISCVMXL cpu_address_xl(CPURISCVState *env)
794
}
795
#endif
796
797
-static inline int riscv_cpu_xlen(CPURISCVState *env)
797
+static inline uint16_t riscv_cpu_xlen(CPURISCVState *env)
798
{
799
return 16 << env->xl;
800
}
target/riscv/csr.c
+16
-16
@@ -2440,7 +2440,7 @@ static RISCVException rmw_xiselect(CPURISCVState *env, int csrno,
2440
target_ulong *val, target_ulong new_val,
2441
target_ulong wr_mask)
2442
{
2443
- target_ulong *iselect;
2443
+ uint16_t *iselect;
2444
int ret;
2445
2446
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT);
@@ -2483,18 +2483,18 @@ static RISCVException rmw_xiselect(CPURISCVState *env, int csrno,
2483
return RISCV_EXCP_NONE;
2484
}
2485
2486
-static bool xiselect_aia_range(target_ulong isel)
2486
+static bool xiselect_aia_range(uint16_t isel)
2487
{
2488
return (ISELECT_IPRIO0 <= isel && isel <= ISELECT_IPRIO15) ||
2489
(ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST);
2490
}
2491
2492
-static bool xiselect_cd_range(target_ulong isel)
2492
+static bool xiselect_cd_range(uint16_t isel)
2493
{
2494
return (ISELECT_CD_FIRST <= isel && isel <= ISELECT_CD_LAST);
2495
}
2496
2497
-static bool xiselect_ctr_range(int csrno, target_ulong isel)
2497
+static bool xiselect_ctr_range(int csrno, uint16_t isel)
2498
{
2499
/* MIREG-MIREG6 for the range 0x200-0x2ff are not used by CTR. */
2500
return CTR_ENTRIES_FIRST <= isel && isel <= CTR_ENTRIES_LAST &&
@@ -2502,7 +2502,7 @@ static bool xiselect_ctr_range(int csrno, target_ulong isel)
2502
}
2503
2504
static int rmw_iprio(target_ulong xlen,
2505
- target_ulong iselect, uint8_t *iprio,
2505
+ uint16_t iselect, uint8_t *iprio,
2506
target_ulong *val, target_ulong new_val,
2507
target_ulong wr_mask, int ext_irq_no)
2508
{
@@ -2546,7 +2546,7 @@ static int rmw_iprio(target_ulong xlen,
2546
return 0;
2547
}
2548
2549
-static int rmw_ctrsource(CPURISCVState *env, int isel, target_ulong *val,
2549
+static int rmw_ctrsource(CPURISCVState *env, uint16_t isel, target_ulong *val,
2550
target_ulong new_val, target_ulong wr_mask)
2551
{
2552
/*
@@ -2585,7 +2585,7 @@ static int rmw_ctrsource(CPURISCVState *env, int isel, target_ulong *val,
2585
return 0;
2586
}
2587
2588
-static int rmw_ctrtarget(CPURISCVState *env, int isel, target_ulong *val,
2588
+static int rmw_ctrtarget(CPURISCVState *env, uint16_t isel, target_ulong *val,
2589
target_ulong new_val, target_ulong wr_mask)
2590
{
2591
/*
@@ -2624,7 +2624,7 @@ static int rmw_ctrtarget(CPURISCVState *env, int isel, target_ulong *val,
2624
return 0;
2625
}
2626
2627
-static int rmw_ctrdata(CPURISCVState *env, int isel, target_ulong *val,
2627
+static int rmw_ctrdata(CPURISCVState *env, uint16_t isel, target_ulong *val,
2628
target_ulong new_val, target_ulong wr_mask)
2629
{
2630
/*
@@ -2665,7 +2665,7 @@ static int rmw_ctrdata(CPURISCVState *env, int isel, target_ulong *val,
2665
}
2666
2667
static RISCVException rmw_xireg_aia(CPURISCVState *env, int csrno,
2668
- target_ulong isel, target_ulong *val,
2668
+ uint16_t isel, target_ulong *val,
2669
target_ulong new_val, target_ulong wr_mask)
2670
{
2671
bool virt = false, isel_reserved = false;
@@ -2746,12 +2746,12 @@ done:
2746
}
2747
2748
static int rmw_xireg_cd(CPURISCVState *env, int csrno,
2749
- target_ulong isel, target_ulong *val,
2749
+ uint16_t isel, target_ulong *val,
2750
target_ulong new_val, target_ulong wr_mask)
2751
{
2752
int ret = -EINVAL;
2753
- int ctr_index = isel - ISELECT_CD_FIRST;
2754
- int isel_hpm_start = ISELECT_CD_FIRST + 3;
2753
+ uint16_t ctr_index = isel - ISELECT_CD_FIRST;
2754
+ uint16_t isel_hpm_start = ISELECT_CD_FIRST + 3;
2755
2756
if (!riscv_cpu_cfg(env)->ext_smcdeleg || !riscv_cpu_cfg(env)->ext_ssccfg) {
2757
ret = RISCV_EXCP_ILLEGAL_INST;
@@ -2818,7 +2818,7 @@ done:
2818
}
2819
2820
static int rmw_xireg_ctr(CPURISCVState *env, int csrno,
2821
- target_ulong isel, target_ulong *val,
2821
+ uint16_t isel, target_ulong *val,
2822
target_ulong new_val, target_ulong wr_mask)
2823
{
2824
if (!riscv_cpu_cfg(env)->ext_smctr && !riscv_cpu_cfg(env)->ext_ssctr) {
@@ -2846,7 +2846,7 @@ static int rmw_xireg_ctr(CPURISCVState *env, int csrno,
2846
* extension using csrind should be implemented here.
2847
*/
2848
static int rmw_xireg_csrind(CPURISCVState *env, int csrno,
2849
- target_ulong isel, target_ulong *val,
2849
+ uint16_t isel, target_ulong *val,
2850
target_ulong new_val, target_ulong wr_mask)
2851
{
2852
bool virt = csrno == CSR_VSIREG ? true : false;
@@ -2876,7 +2876,7 @@ static int rmw_xiregi(CPURISCVState *env, int csrno, target_ulong *val,
2876
target_ulong new_val, target_ulong wr_mask)
2877
{
2878
int ret = -EINVAL;
2879
- target_ulong isel;
2879
+ uint16_t isel;
2880
2881
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT);
2882
if (ret != RISCV_EXCP_NONE) {
@@ -2907,7 +2907,7 @@ static RISCVException rmw_xireg(CPURISCVState *env, int csrno,
2907
target_ulong wr_mask)
2908
{
2909
int ret = -EINVAL;
2910
- target_ulong isel;
2910
+ uint16_t isel;
2911
2912
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT);
2913
if (ret != RISCV_EXCP_NONE) {
target/riscv/machine.c
+3
-3
@@ -109,7 +109,7 @@ static const VMStateDescription vmstate_hyper = {
109
VMSTATE_UINT64(env.vscause, RISCVCPU),
110
VMSTATE_UINT64(env.vstval, RISCVCPU),
111
VMSTATE_UINT64(env.vsatp, RISCVCPU),
112
- VMSTATE_UINTTL(env.vsiselect, RISCVCPU),
112
+ VMSTATE_UINT16(env.vsiselect, RISCVCPU),
113
VMSTATE_UINT64(env.vsie, RISCVCPU),
114
115
VMSTATE_UINT64(env.mtval2, RISCVCPU),
@@ -487,8 +487,8 @@ const VMStateDescription vmstate_riscv_cpu = {
487
VMSTATE_UINT64(env.mepc, RISCVCPU),
488
VMSTATE_UINT64(env.mcause, RISCVCPU),
489
VMSTATE_UINT64(env.mtval, RISCVCPU),
490
- VMSTATE_UINTTL(env.miselect, RISCVCPU),
491
- VMSTATE_UINTTL(env.siselect, RISCVCPU),
490
+ VMSTATE_UINT16(env.miselect, RISCVCPU),
491
+ VMSTATE_UINT16(env.siselect, RISCVCPU),
492
VMSTATE_UINT32(env.scounteren, RISCVCPU),
493
VMSTATE_UINT32(env.mcounteren, RISCVCPU),
494
VMSTATE_UINT32(env.scountinhibit, RISCVCPU),