target/arm: Implement FEAT_FAMINMAX for AdvSIMD
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260522220306.235200-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
May 22, 2026 at 15:02 UTC
dbbcf746c2b080cc719cacba5a3785915950183f
6 files changed
+76
target/arm/cpu-features.h
+5
@@ -1062,6 +1062,11 @@ static inline bool isar_feature_aa64_ats1a(const ARMISARegisters *id)
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return FIELD_EX64_IDREG(id, ID_AA64ISAR2, ATS1A);
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}
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+static inline bool isar_feature_aa64_faminmax(const ARMISARegisters *id)
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+{
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+ return FIELD_EX64_IDREG(id, ID_AA64ISAR3, FAMINMAX) != 0;
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+}
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+
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static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
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{
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/* We always set the AdvSIMD and FP fields identically. */
target/arm/tcg/a64.decode
+5
@@ -1193,6 +1193,11 @@ RSUBHN 0.10 1110 ..1 ..... 01100 0 ..... ..... @qrrr_e
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PMULL_p8 0.00 1110 001 ..... 11100 0 ..... ..... @qrrr_b
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PMULL_p64 0.00 1110 111 ..... 11100 0 ..... ..... @qrrr_b
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+FAMAX 0.00 1110 110 ..... 00011 1 ..... ..... @qrrr_h
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+FAMAX 0.00 1110 1.1 ..... 11011 1 ..... ..... @qrrr_sd
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+FAMIN 0.10 1110 110 ..... 00011 1 ..... ..... @qrrr_h
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+FAMIN 0.10 1110 1.1 ..... 11011 1 ..... ..... @qrrr_sd
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+
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### Advanced SIMD scalar x indexed element
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FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h
target/arm/tcg/helper-a64-defs.h
+7
@@ -145,6 +145,13 @@ DEF_HELPER_FLAGS_5(gvec_fmulx_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst,
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DEF_HELPER_FLAGS_5(gvec_fmulx_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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DEF_HELPER_FLAGS_5(gvec_fmulx_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_5(gvec_famax_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_5(gvec_famin_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_5(gvec_famax_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_5(gvec_famin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_5(gvec_famax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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+DEF_HELPER_FLAGS_5(gvec_famin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
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+
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#ifndef CONFIG_USER_ONLY
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DEF_HELPER_2(exception_return, void, env, i64)
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#endif
target/arm/tcg/translate-a64.c
+14
@@ -6475,6 +6475,20 @@ static gen_helper_gvec_3_ptr * const f_vector_fminnmp[3] = {
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};
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TRANS(FMINNMP_v, do_fp3_vector, a, 0, f_vector_fminnmp)
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+static gen_helper_gvec_3_ptr * const f_vector_famax[3] = {
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+ gen_helper_gvec_famax_h,
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+ gen_helper_gvec_famax_s,
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+ gen_helper_gvec_famax_d,
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+};
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+TRANS_FEAT(FAMAX, aa64_faminmax, do_fp3_vector, a, 0, f_vector_famax)
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+
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+static gen_helper_gvec_3_ptr * const f_vector_famin[3] = {
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+ gen_helper_gvec_famin_h,
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+ gen_helper_gvec_famin_s,
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+ gen_helper_gvec_famin_d,
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+};
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+TRANS_FEAT(FAMIN, aa64_faminmax, do_fp3_vector, a, 0, f_vector_famin)
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+
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static bool do_fmlal(DisasContext *s, arg_qrrr_e *a, bool is_s, bool is_2)
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{
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if (fp_access_check(s)) {
target/arm/tcg/vec_helper64.c
+38
@@ -8,6 +8,7 @@
8
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#include "qemu/osdep.h"
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#include "cpu.h"
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+#include "internals.h"
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#include "helper.h"
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#include "helper-a64.h"
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#include "helper-sme.h"
@@ -140,3 +141,40 @@ void HELPER(simd_tblx)(void *vd, void *vm, CPUARMState *env, uint32_t desc)
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memcpy(vd, &result, 16);
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clear_tail(vd, oprsz, simd_maxsz(desc));
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}
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+
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+/*
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+ * Use float_minmax_ismag to get the absolute value min/max.
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+ * Avoid float_minmax_is{num,number} so that we get normal NaN processing.
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+ * If the result is not a nan, take the absolute value.
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+ *
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+ * Note this operation squashes FZ, FIZ, and AH to 0.
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+ */
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+#define DO_FAMINMAX(NAME, TYPE, MIN) \
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+TYPE TYPE##_##NAME(TYPE a, TYPE b, float_status *s) \
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+{ \
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+ float_status local = *s; \
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+ set_flush_to_zero(false, &local); \
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+ set_flush_inputs_to_zero(false, &local); \
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+ arm_set_default_fp_behaviours(&local); \
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+ TYPE r = TYPE##_minmax(a, b, &local, MIN | float_minmax_ismag); \
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+ if (!TYPE##_is_any_nan(r)) { \
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+ r = TYPE##_abs(r); \
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+ } \
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+ float_raise(get_float_exception_flags(&local) \
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+ & ~float_flag_input_denormal_used, s); \
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+ return r; \
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+}
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+
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+DO_FAMINMAX(famax, float16, 0)
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+DO_FAMINMAX(famin, float16, float_minmax_ismin)
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+DO_FAMINMAX(famax, float32, 0)
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+DO_FAMINMAX(famin, float32, float_minmax_ismin)
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+DO_FAMINMAX(famax, float64, 0)
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+DO_FAMINMAX(famin, float64, float_minmax_ismin)
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+
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+DO_3OP(gvec_famax_h, float16_famax, float16)
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+DO_3OP(gvec_famin_h, float16_famin, float16)
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+DO_3OP(gvec_famax_s, float32_famax, float32)
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+DO_3OP(gvec_famin_s, float32_famin, float32)
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+DO_3OP(gvec_famax_d, float64_famax, float64)
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+DO_3OP(gvec_famin_d, float64_famin, float64)
target/arm/tcg/vec_internal.h
+7
@@ -342,6 +342,13 @@ bfloat16 helper_sme2_ah_fmin_b16(bfloat16 a, bfloat16 b, float_status *fpst);
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float32 sve_f16_to_f32(float16 f, float_status *fpst);
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float16 sve_f32_to_f16(float32 f, float_status *fpst);
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+float16 float16_famax(float16, float16, float_status *);
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+float16 float16_famin(float16, float16, float_status *);
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+float32 float32_famax(float32, float32, float_status *);
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+float32 float32_famin(float32, float32, float_status *);
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+float64 float64_famax(float64, float64, float_status *);
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+float64 float64_famin(float64, float64, float_status *);
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+
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/*
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* Decode helper functions for predicate as counter.
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*/