target/riscv: Apply UXL WARL handling to vsstatus
write_mstatus() already handles the reserved UXL value by writing a legal value instead. Apply the same handling when writing vsstatus so that reserved UXL values follow the same WARL behavior. Factor the common logic into a local helper riscv_write_uxl() and use it for both mstatus and vsstatus. Suggested-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Fixes: f310df58bd2 ("target/riscv: Enable uxl field write") Signed-off-by: SeungJu Cheon <suunj1331@gmail.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Message-ID: <20260625081521.595683-1-suunj1331@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
SeungJu Cheon committed
Jun 25, 2026 at 17:15 UTC
dcd028517749835a618bb1fe8dca32d82318e1c1
1 file changed
+17
-10
target/riscv/csr.c
+17
-10
@@ -2021,6 +2021,20 @@ static target_ulong legalize_mpp(CPURISCVState *env, target_ulong old_mpp,
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return val;
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}
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+static uint64_t riscv_write_uxl(CPURISCVState *env, uint64_t val,
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+ uint64_t field)
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+{
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+ RISCVMXL xl = riscv_cpu_mxl(env);
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+ uint64_t uxl = get_field(val, field);
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+
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+ if (uxl == MXL_RV128) {
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+ uxl = xl == MXL_RV128 ? MXL_RV64 : xl;
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+ val = set_field(val, field, uxl);
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+ }
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+
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+ return val;
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+}
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+
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static RISCVException write_mstatus(CPURISCVState *env, int csrno,
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target_ulong val, uintptr_t ra)
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{
@@ -2067,17 +2081,8 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
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if (xl != MXL_RV32 || env->debugger) {
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if ((val & MSTATUS64_UXL) != 0) {
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- uint64_t uxl = val & MSTATUS64_UXL >> 32;
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mask |= MSTATUS64_UXL;
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-
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- /*
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- * uxl = 3 is reserved so write the current xl instead.
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- * In case xl = MXL_RV128 (3) write MXL_RV64.
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- */
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- if (uxl == 3) {
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- uxl = xl == MXL_RV128 ? MXL_RV64 : xl;
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- val = deposit64(val, 32, 2, uxl);
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- }
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+ val = riscv_write_uxl(env, val, MSTATUS64_UXL);
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}
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}
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@@ -5239,6 +5244,8 @@ static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
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uint64_t mask = (target_ulong)-1;
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if ((val & VSSTATUS64_UXL) == 0) {
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mask &= ~VSSTATUS64_UXL;
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+ } else {
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+ val = riscv_write_uxl(env, val, VSSTATUS64_UXL);
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}
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if ((env->henvcfg & HENVCFG_DTE)) {
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if ((val & SSTATUS_SDT) != 0) {