@samitouri / QOSamiQemu / commits / dd3a906d35

linux-user/mips64: fix elf_core_copy_regs register layout in core files

mips64/elfload.c uses #include "../mips/elfload.c" to share code. When the compiler processes mips/elfload.c the quoted #include "target_elf.h" resolves relative to the including file's directory, so it picks up mips/target_elf.h instead of mips64/target_elf.h. mips/target_elf.h pulls in mips/target_ptrace.h, whose target_pt_regs has a pad0[6] field before regs[]. As a result elf_core_copy_regs writes: r->pt.regs[i] -> reserved[6+i] (shifted by 6 from the correct index) r->pt.cp0_epc -> reserved[40] (correct mips64 N64 index is 34) The Linux kernel and glibc both use the mips64 N64 layout (no pad0): EPC at reserved[34]. Debuggers and libunwind reading the core with N64 constants therefore see a completely wrong register set — EPC points to GP, RA holds the branch target instead of the link address, etc. Fix by: - Guarding the mips32 elf_core_copy_regs in mips/elfload.c with #ifndef TARGET_MIPS64 so it is not compiled for mips64/mipsn32 targets. - Providing a mips64-specific elf_core_copy_regs in mips64/elfload.c that writes directly to r->reserved[i] with the correct N64 indices, bypassing the struct field names that are tainted by the wrong header include. The mipsn32 (TARGET_ABI_MIPSN32) and mips64el targets are covered by the same mips64/elfload.c and benefit from the same fix. Signed-off-by: Matt Turner <mattst88@gmail.com> Cc: qemu-stable@nongnu.org Signed-off-by: Helge Deller <deller@gmx.de>

Matt Turner committed May 21, 2026 at 14:41 UTC dd3a906d3505561d9cb3367b82c5475acca50b6b
2 files changed +31
linux-user/mips/elfload.c
+2
@@ -131,6 +131,7 @@ const char *get_elf_base_platform(CPUState *cs)
131 #undef MATCH_PLATFORM_INSN
132
133 /* See linux kernel: arch/mips/kernel/process.c:elf_dump_regs. */
134 +#ifndef TARGET_MIPS64
135 void elf_core_copy_regs(target_elf_gregset_t *r, const CPUMIPSState *env)
136 {
137 for (int i = 1; i < ARRAY_SIZE(env->active_tc.gpr); i++) {
@@ -146,3 +147,4 @@ void elf_core_copy_regs(target_elf_gregset_t *r, const CPUMIPSState *env)
147 r->pt.cp0_status = tswapl(env->CP0_Status);
148 r->pt.cp0_cause = tswapl(env->CP0_Cause);
149 }
150 +#endif
linux-user/mips64/elfload.c
+29
@@ -1 +1,30 @@
1 #include "../mips/elfload.c"
2 +
3 +/*
4 + * mips/elfload.c defines elf_core_copy_regs guarded by #ifndef TARGET_MIPS64.
5 + *
6 + * We must provide the mips64 version here. We cannot use r->pt.regs[] because
7 + * when mips/elfload.c is #include'd above its "#include "target_elf.h"" resolves
8 + * to mips/target_elf.h (compiler searches the including file's directory first),
9 + * which pulls in mips/target_ptrace.h. That struct has pad0[6] before regs[],
10 + * so r->pt.regs[i] writes to reserved[6+i] — offset by 6 from what the kernel
11 + * and glibc expect for the N64 ABI (EPC at reserved[34], not reserved[40]).
12 + *
13 + * Write directly to reserved[] using the mips64 N64 index layout:
14 + * R0-R31 at reserved[0..31], LO at [32], HI at [33], EPC at [34].
15 + */
16 +void elf_core_copy_regs(target_elf_gregset_t *r, const CPUMIPSState *env)
17 +{
18 + /* R0 is always 0; r->reserved is zero-initialised by the caller */
19 + for (int i = 1; i < 32; i++) {
20 + r->reserved[i] = tswap64(env->active_tc.gpr[i]);
21 + }
22 + r->reserved[26] = 0; /* k0 */
23 + r->reserved[27] = 0; /* k1 */
24 + r->reserved[32] = tswap64(env->active_tc.LO[0]);
25 + r->reserved[33] = tswap64(env->active_tc.HI[0]);
26 + r->reserved[34] = tswap64(env->active_tc.PC);
27 + r->reserved[35] = tswap64(env->CP0_BadVAddr);
28 + r->reserved[36] = tswap64(env->CP0_Status);
29 + r->reserved[37] = tswap64(env->CP0_Cause);
30 +}