disas/riscv: enable `mnret` disassembly
The translator has supported mnret since commit 3157a553ec6b9a ("target/riscv: Add Smrnmi mnret instruction"), but the disassembler still renders it as illegal. Add it unguarded, since the encoding does not overlap any other extension. Signed-off-by: imaginos <imaginos32@gmail.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260614141315.17320-1-imaginos32@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
imaginos committed
Jun 14, 2026 at 16:12 UTC
dd595103dbe27ed6f44382fb4d4bb4b5e88d90a5
1 file changed
+7
disas/riscv.c
+7
@@ -989,6 +989,7 @@ typedef enum {
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rv_op_cbo_clean = 957,
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rv_op_cbo_flush = 958,
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rv_op_cbo_zero = 959,
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+ rv_op_mnret = 960,
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} rv_op;
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/* register names */
@@ -2263,6 +2264,7 @@ const rv_opcode_data rvi_opcode_data[] = {
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{ "cbo.clean", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
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{ "cbo.flush", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
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{ "cbo.zero", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
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+ { "mnret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
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};
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/* CSR names */
@@ -4077,6 +4079,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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case 64: op = rv_op_mret; break;
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}
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break;
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+ case 1792:
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+ switch ((inst >> 15) & 0b1111111111) {
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+ case 64: op = rv_op_mnret; break;
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+ }
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+ break;
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case 1952:
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switch ((inst >> 15) & 0b1111111111) {
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case 576: op = rv_op_dret; break;