target/arm: Implement FCVT, FCVTN (FP32 to FP8) for SME
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260609192110.752384-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 9, 2026 at 12:20 UTC
deadb7c6e88286e992df1cbf078c74dce3302828
4 files changed
+67
target/arm/tcg/fp8_helper.c
+59
@@ -509,3 +509,62 @@ void HELPER(sve2_fcvtnt_bs)(void *vd, void *vn, CPUARMState *env, uint32_t desc)
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fp8_cvt_finish(env, &ctx);
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}
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+
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+void HELPER(sme2_fcvt_bs)(void *vd, void *vn, CPUARMState *env, uint32_t desc)
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+{
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+ ARMVectorReg scratch[4];
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+ FP8Context ctx = fp8_dst_start(env, desc, false);
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+ fcvt_fp8_output_fn *output_fmt = fcvt_fp8_output_fmt[ctx.f8fmt];
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+ uint32_t *n = vn;
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+ uint8_t *d = vd;
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+ bool osc = FIELD_EX64(env->vfp.fpmr, FPMR, OSC);
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+ size_t oprsz = simd_oprsz(desc);
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+ size_t nelem = oprsz / 4;
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+ size_t stride = sizeof(ARMVectorReg) / 4;
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+
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+ if (vectors_overlap(vd, 1, vn, 4)) {
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+ n = memcpy(scratch, vn, sizeof(scratch));
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+ }
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+
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+ for (size_t i = 0; i < nelem; i++) {
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+ for (size_t j = 0; j < 4; j++) {
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+ d[H1(i + nelem * j)] = fcvt_f32_to_fp8(n[H4(i) + stride * j],
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+ output_fmt, ctx.scale,
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+ osc, &ctx.stat);
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+ }
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+ }
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+
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+ fp8_cvt_finish(env, &ctx);
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+}
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+
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+void HELPER(sme2_fcvtn_bs)(void *vd, void *vn, CPUARMState *env, uint32_t desc)
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+{
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+ FP8Context ctx = fp8_dst_start(env, desc, false);
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+ fcvt_fp8_output_fn *output_fmt = fcvt_fp8_output_fmt[ctx.f8fmt];
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+ uint32_t *n0 = vn;
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+ uint32_t *n1 = vn + sizeof(ARMVectorReg);
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+ uint32_t *n2 = vn + sizeof(ARMVectorReg) * 2;
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+ uint32_t *n3 = vn + sizeof(ARMVectorReg) * 3;
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+ uint8_t *d = vd;
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+ bool osc = FIELD_EX64(env->vfp.fpmr, FPMR, OSC);
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+ size_t oprsz = simd_oprsz(desc);
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+ size_t nelem = oprsz / 4;
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+
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+ for (size_t i = 0; i < nelem; ++i) {
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+ float32 e0 = n0[H4(i)];
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+ float32 e1 = n1[H4(i)];
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+ float32 e2 = n2[H4(i)];
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+ float32 e3 = n3[H4(i)];
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+
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+ d[H1(4 * i + 0)] = fcvt_f32_to_fp8(e0, output_fmt,
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+ ctx.scale, osc, &ctx.stat);
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+ d[H1(4 * i + 1)] = fcvt_f32_to_fp8(e1, output_fmt,
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+ ctx.scale, osc, &ctx.stat);
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+ d[H1(4 * i + 2)] = fcvt_f32_to_fp8(e2, output_fmt,
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+ ctx.scale, osc, &ctx.stat);
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+ d[H1(4 * i + 3)] = fcvt_f32_to_fp8(e3, output_fmt,
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+ ctx.scale, osc, &ctx.stat);
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+ }
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+
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+ fp8_cvt_finish(env, &ctx);
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+}
target/arm/tcg/helper-fp8-defs.h
+2
@@ -21,3 +21,5 @@ DEF_HELPER_FLAGS_4(sve2_fcvtn_bh, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
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DEF_HELPER_FLAGS_5(advsimd_fcvt_bs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
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DEF_HELPER_FLAGS_4(sve2_fcvtnb_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
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DEF_HELPER_FLAGS_4(sve2_fcvtnt_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
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+DEF_HELPER_FLAGS_4(sme2_fcvt_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
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+DEF_HELPER_FLAGS_4(sme2_fcvtn_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
target/arm/tcg/sme.decode
+3
@@ -865,6 +865,9 @@ BF2CVTL 11000001 111 00110 111000 ..... ....1 @zz_2x1
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FCVT_bh 11000001 001 00100 111000 ....0 ..... @zz_1x2
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+FCVT_bs 11000001 001 10100 111000 ...00 ..... @zz_1x4
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+FCVTN_bs 11000001 001 10100 111000 ...01 ..... @zz_1x4
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+
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ZIP_4 11000001 esz:2 1 10110 111000 ...00 ... 00 \
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&zz_e zd=%zd_ax4 zn=%zn_ax4
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ZIP_4 11000001 001 10111 111000 ...00 ... 00 \
target/arm/tcg/translate-sme.c
+3
@@ -1572,6 +1572,9 @@ static bool trans_FCVT_bh(DisasContext *s, arg_zz_n *a)
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return true;
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}
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+TRANS_FEAT(FCVT_bs, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_fcvt_bs, 0)
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+TRANS_FEAT(FCVTN_bs, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_fcvtn_bs, 0)
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+
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static bool do_zipuzp_4(DisasContext *s, arg_zz_e *a,
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gen_helper_gvec_2 * const fn[5])
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{