target/arm: Implement PMULL, PMLAL
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260826174213.614571-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Aug 26, 2026 at 10:42 UTC
df63b69b8d12a97487e063128c324d25dbcdae4e
4 files changed
+47
target/arm/tcg/helper-sve-defs.h
+3
@@ -3215,3 +3215,6 @@ DEF_HELPER_FLAGS_4(sve_expand_b, TCG_CALL_NO_WG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_expand_h, TCG_CALL_NO_WG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_expand_s, TCG_CALL_NO_WG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_expand_d, TCG_CALL_NO_WG, void, ptr, ptr, ptr, i32)
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+
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+DEF_HELPER_FLAGS_4(sve_pmull_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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+DEF_HELPER_FLAGS_4(sve_pmlal_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
target/arm/tcg/sve.decode
+5
@@ -1994,6 +1994,11 @@ AESEMC 01000101 00 1 .. .11111010 ..... ...00 @aes2_4
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AESDIMC 01000101 00 1 .. .11111011 ..... ....0 @aes2_2
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AESDIMC 01000101 00 1 .. .11111011 ..... ...00 @aes2_4
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+PMULL 01000101 00 1 rm:5 111110 rn:5 ....0 \
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+ &rrr_esz esz=0 rd=%zd_ax2
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+PMLAL 01000101 00 1 rm:5 111111 rn:5 ....0 \
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+ &rrr_esz esz=0 rd=%zd_ax2
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+
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# SVE2 crypto constructive binary operations
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SM4EKEY 01000101 00 1 ..... 11110 0 ..... ..... @rd_rn_rm_e0
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RAX1 01000101 00 1 ..... 11110 1 ..... ..... @rd_rn_rm_e0
target/arm/tcg/translate-sve.c
+5
@@ -8351,6 +8351,11 @@ TRANS_FEAT_STREAMING_IF(AESEMC, aa64_sve_aes2, aa64_ssve_aes,
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TRANS_FEAT_STREAMING_IF(AESDIMC, aa64_sve_aes2, aa64_ssve_aes,
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do_aes2_idx, a, gen_helper_crypto_aesdimc)
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+TRANS_FEAT_STREAMING_IF(PMULL, aa64_sve_aes2, aa64_ssve_aes,
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+ gen_gvec_ool_arg_zzz, gen_helper_sve_pmull_q, a, 0)
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+TRANS_FEAT_STREAMING_IF(PMLAL, aa64_sve_aes2, aa64_ssve_aes,
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+ gen_gvec_ool_arg_zzz, gen_helper_sve_pmlal_q, a, 0)
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+
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TRANS_FEAT(FCVTNT_sh_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz,
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gen_helper_sve2_fcvtnt_sh, a, 0, FPST_A64)
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TRANS_FEAT(FCVTNT_sh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz,
target/arm/tcg/vec_helper64.c
+34
@@ -89,6 +89,40 @@ void HELPER(sve2_pmull_d)(void *vd, void *vn, void *vm, uint32_t desc)
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}
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}
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+void HELPER(sve_pmull_q)(void *vd, void *vn, void *vm, uint32_t desc)
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+{
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+ intptr_t opr_sz = simd_oprsz(desc);
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+ uint64_t *n = vn, *m = vm;
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+ uint64_t *d0 = vd;
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+ uint64_t *d1 = vd + sizeof(ARMVectorReg);
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+
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+ for (intptr_t i = 0; i < opr_sz / 16; ++i) {
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+ Int128 rl = clmul_64(n[2 * i + 0], m[2 * i + 0]);
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+ Int128 rh = clmul_64(n[2 * i + 1], m[2 * i + 1]);
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+ d0[2 * i + 0] = int128_getlo(rl);
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+ d0[2 * i + 1] = int128_gethi(rl);
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+ d1[2 * i + 0] = int128_getlo(rh);
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+ d1[2 * i + 1] = int128_gethi(rh);
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+ }
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+}
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+
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+void HELPER(sve_pmlal_q)(void *vd, void *vn, void *vm, uint32_t desc)
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+{
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+ intptr_t opr_sz = simd_oprsz(desc);
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+ uint64_t *n = vn, *m = vm;
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+ uint64_t *d0 = vd;
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+ uint64_t *d1 = vd + sizeof(ARMVectorReg);
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+
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+ for (intptr_t i = 0; i < opr_sz / 16; ++i) {
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+ Int128 rl = clmul_64(n[2 * i + 0], m[2 * i + 0]);
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+ Int128 rh = clmul_64(n[2 * i + 1], m[2 * i + 1]);
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+ d0[2 * i + 0] ^= int128_getlo(rl);
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+ d0[2 * i + 1] ^= int128_gethi(rl);
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+ d1[2 * i + 0] ^= int128_getlo(rh);
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+ d1[2 * i + 1] ^= int128_gethi(rh);
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+ }
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+}
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+
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DO_3OP_PAIR(gvec_ah_fmaxp_h, helper_vfp_ah_maxh, float16, H2)
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DO_3OP_PAIR(gvec_ah_fmaxp_s, helper_vfp_ah_maxs, float32, H4)
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DO_3OP_PAIR(gvec_ah_fmaxp_d, helper_vfp_ah_maxd, float64, /**/)