docs/system: declare support for FEAT_EVT2
The actual implementation supports the additional trapping registers of HCR_TTLBIS | HCR_TTLBOS. We already set the value to 2 for -cpu max and don't currently model any CPUs that only have FEAT_EVT. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260708145841.3032079-2-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alex Bennée committed
Jul 13, 2026 at 12:34 UTC
e0f0c89c942bbb73fe77f10ccf2367e6e709716d
2 files changed
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-1
docs/system/arm/emulation.rst
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@@ -68,6 +68,7 @@ the following architecture extensions:
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- FEAT_EPAC (Enhanced pointer authentication)
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- FEAT_ETS2 (Enhanced Translation Synchronization)
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- FEAT_EVT (Enhanced Virtualization Traps)
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+- FEAT_EVT2 (Enhanced Virtualization Traps 2)
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- FEAT_F8F16MM (8-bit floating-point matrix multiply-accumulate to half-precision)
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- FEAT_F8F32MM (8-bit floating-point matrix multiply-accumulate to single-precision)
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- FEAT_F32MM (Single-precision Matrix Multiplication)
target/arm/cpu-max.c
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@@ -130,7 +130,7 @@ void aa32_max_features(ARMCPU *cpu)
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t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
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t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
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t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
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- t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */
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+ t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT2 */
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SET_IDREG(isar, ID_MMFR4, t);
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FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */