target/riscv: Support raising misaligned exceptions for floating-point loads/stores
When the Zicclsm extension is not enabled, raise misaligned load/store exceptions for misaligned accesses from floating-point load/store instructions (RVF, RVD, Zfh). Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Message-ID: <20260810055618.1175500-5-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang committed
Aug 10, 2026 at 13:56 UTC
e1322e1558ac9b2547baa2eb9b5b924220e89910
3 files changed
+18
target/riscv/tcg/insn_trans/trans_rvd.c.inc
+6
@@ -61,6 +61,9 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
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memop |= MO_ATOM_IFALIGN;
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}
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memop |= ctx->mo_endianness;
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+ if (!ctx->cfg_ptr->ext_zicclsm) {
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+ memop |= MO_ALIGN;
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+ }
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decode_save_opc(ctx, 0);
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addr = get_address(ctx, a->rs1, a->imm);
@@ -86,6 +89,9 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
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memop |= MO_ATOM_IFALIGN;
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}
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memop |= ctx->mo_endianness;
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+ if (!ctx->cfg_ptr->ext_zicclsm) {
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+ memop |= MO_ALIGN;
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+ }
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decode_save_opc(ctx, 0);
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addr = get_address(ctx, a->rs1, a->imm);
target/riscv/tcg/insn_trans/trans_rvf.c.inc
+6
@@ -52,6 +52,9 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
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if (ctx->cfg_ptr->ext_zama16b) {
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memop |= MO_ATOM_WITHIN16;
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}
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+ if (!ctx->cfg_ptr->ext_zicclsm) {
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+ memop |= MO_ALIGN;
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+ }
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decode_save_opc(ctx, 0);
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addr = get_address(ctx, a->rs1, a->imm);
@@ -75,6 +78,9 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
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if (ctx->cfg_ptr->ext_zama16b) {
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memop |= MO_ATOM_WITHIN16;
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}
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+ if (!ctx->cfg_ptr->ext_zicclsm) {
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+ memop |= MO_ALIGN;
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+ }
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decode_save_opc(ctx, 0);
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addr = get_address(ctx, a->rs1, a->imm);
target/riscv/tcg/insn_trans/trans_rvzfh.c.inc
+6
@@ -50,6 +50,9 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a)
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REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);
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memop |= ctx->mo_endianness;
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+ if (!ctx->cfg_ptr->ext_zicclsm) {
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+ memop |= MO_ALIGN;
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+ }
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decode_save_opc(ctx, 0);
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t0 = get_gpr(ctx, a->rs1, EXT_NONE);
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if (a->imm) {
@@ -75,6 +78,9 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
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REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);
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memop |= ctx->mo_endianness;
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+ if (!ctx->cfg_ptr->ext_zicclsm) {
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+ memop |= MO_ALIGN;
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+ }
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decode_save_opc(ctx, 0);
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t0 = get_gpr(ctx, a->rs1, EXT_NONE);
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if (a->imm) {