target/arm: Implement F1CVTL, F1CVTL2, F2CVTL, F2CVTL2 for AdvSIMD
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260609192110.752384-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 9, 2026 at 12:20 UTC
e167be7970b774bea2ca8da9872d05f1e9ea2018
4 files changed
+37
target/arm/tcg/a64.decode
+3
@@ -1921,6 +1921,9 @@ URSQRTE_v 0.10 1110 101 00001 11001 0 ..... ..... @qrr_s
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FCVTL_v 0.00 1110 0.1 00001 01111 0 ..... ..... @qrr_sd
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+F1CVTL 0.10 1110 001 00001 01111 0 ..... ..... @qrr_h
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+F2CVTL 0.10 1110 011 00001 01111 0 ..... ..... @qrr_h
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+
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BF1CVTL 0.10 1110 101 00001 01111 0 ..... ..... @qrr_h
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BF2CVTL 0.10 1110 111 00001 01111 0 ..... ..... @qrr_h
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target/arm/tcg/fp8_helper.c
+29
@@ -103,6 +103,14 @@ static bfloat16 fcvt_fp8_to_b16(uint8_t x, fp8_input_fn *f8fmt,
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return bfloat16_round_pack_canonical(&p, s);
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}
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+static float16 fcvt_fp8_to_f16(uint8_t x, fp8_input_fn *f8fmt,
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+ int scale, float_status *s)
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+{
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+ FloatParts64 p = f8fmt(x, s);
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+ p = parts64_scalbn(&p, scale, s);
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+ return float16_round_pack_canonical(&p, s);
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+}
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+
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void HELPER(advsimd_bfcvtl)(void *vd, void *vn, CPUARMState *env, uint32_t desc)
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{
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FP8Context ctx = fp8_src_start(env, desc, 0x3f);
@@ -123,6 +131,27 @@ void HELPER(advsimd_bfcvtl)(void *vd, void *vn, CPUARMState *env, uint32_t desc)
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clear_tail(vd, 16, simd_maxsz(desc));
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}
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+void HELPER(advsimd_fcvtl_hb)(void *vd, void *vn,
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+ CPUARMState *env, uint32_t desc)
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+{
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+ FP8Context ctx = fp8_src_start(env, desc, 0xf);
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+ fp8_input_fn *input_fmt = fp8_input_fmt[ctx.f8fmt];
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+ uint8_t *n = vn, scratch[16];
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+ float16 *d = vd;
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+
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+ if (vd == vn) {
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+ n = memcpy(scratch, vn, 16);
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+ }
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+ n += ctx.high * 8;
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+
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+ for (size_t i = 0; i < 8; ++i) {
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+ d[H2(i)] = fcvt_fp8_to_f16(n[H1(i)], input_fmt, ctx.scale, &ctx.stat);
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+ }
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+
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+ fp8_cvt_finish(env, &ctx);
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+ clear_tail(vd, 16, simd_maxsz(desc));
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+}
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+
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void HELPER(sve2_bfcvt)(void *vd, void *vn, CPUARMState *env, uint32_t desc)
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{
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FP8Context ctx = fp8_src_start(env, desc, 0x3f);
target/arm/tcg/helper-fp8-defs.h
+2
@@ -7,3 +7,5 @@ DEF_HELPER_FLAGS_4(advsimd_bfcvtl, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
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DEF_HELPER_FLAGS_4(sve2_bfcvt, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
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DEF_HELPER_FLAGS_4(sme2_bfcvt_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
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DEF_HELPER_FLAGS_4(sme2_bfcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
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+
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+DEF_HELPER_FLAGS_4(advsimd_fcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
target/arm/tcg/translate-a64.c
+3
@@ -10740,6 +10740,9 @@ static bool do_f8cvt(DisasContext *s, arg_qrr_e *a,
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return true;
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}
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+TRANS_FEAT(F1CVTL, aa64_f8cvt, do_f8cvt, a, gen_helper_advsimd_fcvtl_hb, false)
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+TRANS_FEAT(F2CVTL, aa64_f8cvt, do_f8cvt, a, gen_helper_advsimd_fcvtl_hb, true)
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+
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TRANS_FEAT(BF1CVTL, aa64_f8cvt, do_f8cvt, a, gen_helper_advsimd_bfcvtl, false)
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TRANS_FEAT(BF2CVTL, aa64_f8cvt, do_f8cvt, a, gen_helper_advsimd_bfcvtl, true)
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