disas/riscv: Merge all mop.rr.n to one pattern
Avoid performing arithmetic on rv_op_mop_rr_0. Treat the 'n' as an immediate. Create a codec and format to match. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260812223142.349142-48-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Richard Henderson committed
Aug 12, 2026 at 15:31 UTC
e2851825f44e107c1092fca916ee9800ac86380a
3 files changed
+15
-9
disas/riscv-op.c.inc
+1
-8
@@ -874,14 +874,7 @@ OP(amocas_w, "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
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OP(amocas_d, "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
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OP(amocas_q, "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
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OP(mop_r, "mop.r", rv_codec_mop_r, rv_fmt_mop_r)
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-OP(mop_rr_0, "mop.rr.0", rv_codec_r, rv_fmt_rd_rs1_rs2)
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-OP(mop_rr_1, "mop.rr.1", rv_codec_r, rv_fmt_rd_rs1_rs2)
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-OP(mop_rr_2, "mop.rr.2", rv_codec_r, rv_fmt_rd_rs1_rs2)
880
-OP(mop_rr_3, "mop.rr.3", rv_codec_r, rv_fmt_rd_rs1_rs2)
881
-OP(mop_rr_4, "mop.rr.4", rv_codec_r, rv_fmt_rd_rs1_rs2)
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-OP(mop_rr_5, "mop.rr.5", rv_codec_r, rv_fmt_rd_rs1_rs2)
883
-OP(mop_rr_6, "mop.rr.6", rv_codec_r, rv_fmt_rd_rs1_rs2)
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-OP(mop_rr_7, "mop.rr.7", rv_codec_r, rv_fmt_rd_rs1_rs2)
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+OP(mop_rr, "mop.rr", rv_codec_mop_rr, rv_fmt_mop_rr)
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OP(c_mop_1, "c.mop.1", rv_codec_ci_none, rv_fmt_none)
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OP(c_mop_3, "c.mop.3", rv_codec_ci_none, rv_fmt_none)
880
OP(c_mop_5, "c.mop.5", rv_codec_ci_none, rv_fmt_none)
disas/riscv.c
+12
-1
@@ -650,6 +650,11 @@ static uint32_t operand_mop_r_imm(rv_inst inst)
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extract32(inst, 20, 2);
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}
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+static uint32_t operand_mop_rr_imm(rv_inst inst)
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+{
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+ return (extract32(inst, 30, 1) << 2) | extract32(inst, 26, 2);
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+}
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+
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/* instruction metadata */
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static const rv_opcode_data rvi_opcode_data[] = {
@@ -2572,7 +2577,7 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
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== 0b1000001) {
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imm_mop3 = deposit32(extract32(inst, 26, 2),
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2, 1, extract32(inst, 30, 1));
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- op = rv_op_mop_rr_0 + imm_mop3;
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+ op = rv_op_mop_rr;
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/* if zicfiss enabled and mop3 is shadow stack */
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if (dec->cfg->ext_zicfiss &&
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((imm_mop3 & 0b111) == 0b111)) {
@@ -3061,6 +3066,12 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa,
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dec->rs1 = operand_rs1(inst);
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dec->imm = operand_mop_r_imm(inst);
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break;
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+ case rv_codec_mop_rr:
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+ dec->rd = operand_rd(inst);
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+ dec->rs1 = operand_rs1(inst);
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+ dec->rs2 = operand_rs2(inst);
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+ dec->imm = operand_mop_rr_imm(inst);
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+ break;
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default:
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g_assert_not_reached();
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}
disas/riscv.h
+2
@@ -161,6 +161,7 @@ typedef enum {
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rv_codec_lp,
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rv_codec_cmop_ss,
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rv_codec_mop_r,
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+ rv_codec_mop_rr,
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} rv_codec;
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/* structures */
@@ -286,5 +287,6 @@ typedef struct {
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#define rv_fmt_rd2_imm "O\t0,2,(1),i"
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#define rv_fmt_fli "O\t3,h"
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#define rv_fmt_mop_r "O.i\t0,1"
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+#define rv_fmt_mop_rr "O.i\t0,1,2"
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#endif /* DISAS_RISCV_H */